fcb6313187
Add rvb and riscv-tools to rootfs
2024-09-19 11:25:39 +02:00
2fab6b8ec0
Update bitstream to ox_u55c_87a14c32
...
This bitstream attempts to fix the PLIC issues with the threshold
register, so we should see the PLIC tests success now.
See: https://gitlab.bsc.es/hwdesign/fpga/integration-lab/fpga-shell/-/issues/147
2024-09-19 11:01:48 +02:00
5e2430c48b
Disable all firmware from the image
2024-09-19 10:06:48 +02:00
a8859380a6
Use minimal profile
...
Disables a bunch of options, including boot.enableContainers which
removes some unneeded modules from loading.
2024-09-18 18:13:39 +02:00
507f70cf55
Print a message at login
2024-09-18 17:30:59 +02:00
f8cce17fc2
Add riscv-tools to gcroot
2024-09-18 15:48:02 +02:00
b6f15f5b6c
Don't stop the boot after PLIC tests
2024-09-18 15:16:49 +02:00
8846d95281
Load rootfs with fpgactl
2024-09-18 15:14:54 +02:00
b28e317e56
Build the whole system in CI
2024-09-18 15:13:46 +02:00
88a4e239a1
Save commit in shell variable
2024-09-18 15:12:14 +02:00
11ed3dc731
Save GC roots using all drv attributes
2024-09-18 15:03:03 +02:00
71d124815f
Save stdenv in gcroot
2024-09-18 14:35:00 +02:00
4562173d41
Remove commit from U-Boot for now
...
It causes the rebuild of U-Boot and OpenSBI, as we are now bundling the
environment inside the U-Boot image.
2024-09-18 14:30:18 +02:00
877428c2fe
Only save kernel and opensbi build inputs
2024-09-18 14:27:29 +02:00
9daa796b10
Try to save a gcroot will build dependencies
2024-09-18 11:50:55 +02:00
a397ede43d
Switch the default devshell to lagarto-ox-rd
2024-09-12 10:30:56 +02:00
42cd8a46de
Ignore CR in picocom
...
Hopefully this fixes the problem in the live log output of the GitLab CI
where the lines are not displayed.
2024-09-06 09:58:57 +02:00
81e866e68d
Remove unused files
2024-09-06 08:28:51 +02:00
c5b9700655
Move other patched scripts to patches/
2024-09-06 08:27:07 +02:00
3dad4fb3d1
Move patches to its own directory
2024-09-06 08:22:14 +02:00
e2c770208e
Move other tools to tools/
2024-09-06 08:11:24 +02:00
08a304a711
Remove old DT for Lagarto Ox
2024-09-06 07:48:22 +02:00
93edc72700
Don't load the rootfs for now
2024-09-05 17:25:11 +02:00
75ea21f9fe
Move clock comments to lagarto_ox.h
2024-09-05 17:12:35 +02:00
2f48ad5f40
Define DT constants in a C header file
...
Allows writing baremetal programs that can read the correct offsets of
devices or clock frequencies.
2024-09-05 16:59:06 +02:00
5fdaab9f8f
Fix plictest
2024-09-05 15:24:02 +02:00
c6801587b3
Don't load any modules for now
2024-09-05 15:12:44 +02:00
0bcb12a259
Run PLIC test from init directly
2024-09-05 15:06:34 +02:00
4f70ac11ac
Run /preinit before init
2024-09-05 14:57:54 +02:00
ee9ecac8ed
Add PLIC tests to preinit
2024-09-05 14:53:18 +02:00
bbf85438b3
Update journal
2024-09-05 14:53:18 +02:00
d2745c53b1
Prepare preinit for Ethernet
2024-09-05 11:04:51 +02:00
ef0c4d3d94
Set MAC address to zeros
2024-09-05 11:04:16 +02:00
67d57cdd03
Add Xilinx DMA module
2024-09-05 10:06:41 +02:00
bc94e6355f
Fix Ethernet module file name
2024-09-05 10:03:14 +02:00
1787d2cede
Load the modules in initrd
2024-09-05 09:48:36 +02:00
7817c4be2d
Enable DMA node in device tree
2024-09-05 09:44:39 +02:00
6239191835
Add custom Ethernet module
2024-09-05 09:24:19 +02:00
6f12ec6372
Add more PLIC results to the journal
2024-09-05 07:41:32 +02:00
7f1e520270
Improve plictool output and write manual
2024-09-04 16:17:21 +02:00
a6a1d75b7a
Enable debug1 for now
2024-09-04 16:16:26 +02:00
7e48cfe72e
Print contexts in another line with active info
...
Make it clear to determine if a source is configured to emit
interruptions to a given context by printing the active=1 attribute when
the priority is larger than the threshold of the context.
2024-09-04 12:44:53 +02:00
b075d6fa2a
Add problems with the PLIC to the journal
2024-09-04 12:43:46 +02:00
272fd211b2
Adjust RTC frequency to 32786 Hz
2024-09-04 11:46:18 +02:00
158e232520
Update journal
2024-09-04 10:48:48 +02:00
32a7b2f3b7
Enable ethernet node in DT
2024-09-03 16:58:28 +02:00
1620684b8e
Disable aux timer as OpenSBI now fails
2024-09-03 16:14:16 +02:00
fa6227928e
Enable aux timer and test uart in DT
2024-09-03 16:09:53 +02:00
3ee0933d7b
Add plictool to dump PLIC state
2024-09-03 15:59:04 +02:00
1aa899c8f0
Print md5 checksum in fpgactl
2024-09-03 14:59:29 +02:00
