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Enable DMA node in device tree

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This commit is contained in:
Rodrigo Arias 2024-09-05 09:44:39 +02:00
parent 6239191835
commit 7817c4be2d
1 changed files with 38 additions and 40 deletions
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78
ox-plic.dts
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@ -95,12 +95,12 @@
compatible = "shared-dma-pool";
};
};
// eth0_clk: eth0_clk {
// compatible = "fixed-clock";
// #clock-cells = <0x00000000>;
// clock-frequency = <0x09502f90>;
// phandle = <0x00000002>;
// };
dma_clk: dma_clk {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x09502f90>;
phandle = <0x00000002>;
};
pmem@100000000 {
/* volatile; This property indicates that this region is
* actually backed by non-persistent memory. This lets the OS
@ -149,43 +149,41 @@
carv,no-mac;
device_type = "network";
local-mac-address = [02 05 00 01 00 05];
axistream-connected = <0x000000fe>;
//compatible = "xlnx,xxv-ethernet-1.0-carv";
compatible = "xlnx,axi-ethernet-1.00.a";
axistream-connected = <&axi_dma>;
compatible = "xlnx,xxv-ethernet-1.0-carv";
memory-region = <&eth_pool>;
};
// dma@40400000 {
// xlnx,include-dre;
// phandle = <0x000000fe>;
// #dma-cells = <0x00000001>;
// compatible = "xlnx,axi-dma-1.00.a";
// clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
// clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
// reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
// interrupt-names = "mm2s_introut", "s2mm_introut";
// interrupt-parent = <&PLIC>;
// interrupts = <2 3>;
// xlnx,addrwidth = <0x00000028>;
// xlnx,include-sg;
// xlnx,sg-length-width = <0x00000017>;
// dma-channel@40400000 {
// compatible = "xlnx,axi-dma-mm2s-channel";
// dma-channels = <0x00000000>;
// interrupts = <0x00000002>;
// xlnx,datawidth = <0x00000040>;
// xlnx,device-id = <0x00000000>;
// xlnx,include-dre;
// };
// dma-channel@40400030 {
// compatible = "xlnx,axi-dma-s2mm-channel";
// dma-channels = <0x00000001>;
// interrupts = <0x00000003>;
// xlnx,datawidth = <0x00000040>;
// xlnx,device-id = <0x00000000>;
// xlnx,include-dre;
// };
// };
axi_dma: dma@40400000 {
xlnx,include-dre;
#dma-cells = <0x00000001>;
compatible = "xlnx,axi-dma-1.00.a";
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <&dma_clk>, <&dma_clk>, <&dma_clk>, <&dma_clk>;
reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&PLIC>;
interrupts = <2 3>;
xlnx,addrwidth = <0x28>;
xlnx,include-sg;
xlnx,sg-length-width = <0x17>;
dma-channel@40400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0>;
interrupts = <2>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
xlnx,include-dre;
};
dma-channel@40400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <1>;
interrupts = <3>;
xlnx,datawidth = <0x40>;
xlnx,device-id = <0x0>;
xlnx,include-dre;
};
};
/* Platform-Level Interrupt Controller: Delivers interrupts to
* HARTs. */