Commit Graph

35 Commits

Author SHA1 Message Date
fa6227928e Enable aux timer and test uart in DT 2024-09-03 16:09:53 +02:00
a7c6a6f1e6 Add CLINT to device tree at 0x4010_0000 2024-08-30 15:10:46 +02:00
d72b5ff5e9 Disable the CLINT for now 2024-08-30 14:17:55 +02:00
eee26f2b4d More experiments with OpenSBI 1.5 with debug 2024-07-15 11:02:27 +02:00
c38edfe737 Enable PLIC 2024-07-12 18:51:17 +02:00
fc7bfddd64 Switch to openpiton configuration 2024-07-12 18:47:48 +02:00
d3779d0f95 Revert serial address and move FDT 2024-07-12 18:28:43 +02:00
444bb635f6 Move serial to 0x4000_0000 2024-07-12 18:25:14 +02:00
bed3c7ba5c Disable PLIC from DT 2024-07-12 18:19:58 +02:00
8819c091eb Remove clint from device tree for now 2024-07-12 14:57:43 +02:00
97c0dd6859 Remove reserved region hack 2024-07-12 14:50:59 +02:00
8b2821f2f2 Try setting the mtimecmp address 2024-07-12 14:14:25 +02:00
6a57dd004f Switch to "riscv,aclint-mtimer" timer 2024-07-12 13:55:08 +02:00
6604911264 Remove reg-names property from clint 2024-07-12 12:38:34 +02:00
5ddea498ca Add reserved segment from 0x80000000 2024-07-11 15:47:29 +02:00
b7dba89d63 Reduce RAM to 768 MiB to avoid a memory problem 2024-07-10 18:04:11 +02:00
6b3af5b188 Reduce RAM to 1 GiB 2024-07-09 21:11:44 +02:00
4d246ad00e Enable secondary serial console 2024-07-08 10:44:51 +02:00
ef7a100c3f Disable secondary console 2024-07-08 08:49:12 +02:00
6155c7e3f8 Try to fill cache details 2024-07-08 08:48:56 +02:00
05898c5f85 Revert UART speed to 50MHz following vivado log
> UART Name g_UART IntfLabel m_axi_uart SyncClk {Label CLK0 Freq 50000000
> Name clk_i} BaseAddr 0x0 Number 2 AxiAddrWidth 0 AxiDataWidth 0 AxiIdWidth
> 0 AxiUserWidth 0 Mode normal IRQ uart_irq
2024-07-04 17:57:26 +02:00
eb7679f6a2 Prepare device tree to accomodate another UART 2024-07-04 17:22:43 +02:00
fcf4977a65 Extend the serial range from 0x100 to 0x1000
The AXI UART 16550 v2.0 from Xilinx only seem to require 32 bytes for
the registes, but let's reduce the changes with the original DTS.
2024-07-04 16:47:56 +02:00
d5b5cc3363 Change the order of interrupts-extended for PLIC
In the SiFive DTS they are in this order, not sure it that may cause any
difference.
2024-07-04 16:46:35 +02:00
6531fd678c WIP: Test M and S ext interrupt 2024-07-03 20:41:16 +02:00
0c4311e15c Remap interrupts to avoid 0 and duplicates
Let see if we can guess which is the correct number for the interrupts.
The plic should appear in the IRQ list but currently it doesn't.
2024-07-03 18:41:52 +02:00
a40414d08c Add comment about the axi timer
This timer is present and initialized in OpenSBI and seems to drive the
UART device. Not sure if we need to see it from the kernel.
2024-07-03 15:30:28 +02:00
046f017b70 Move the pmem closer to the RAM memory
Continues stuck in switch_root.
2024-07-01 15:02:20 +02:00
763f053f01 Simplify, correct and comment DTS
Disable unused devices and try to fix the interrupt connections. The
compiler dtc doesn't report any warning now.
2024-07-01 11:29:02 +02:00
33b227f576 Hangs in swtich_root in stage1 2024-07-01 10:14:39 +02:00
7b9eb7366e Remove unused PMEM regions
Boots until the init, then fails with:

[   42.561840] Freeing unused kernel image (initmem) memory: 2448K
[   42.572360] Run /init as init process
[   42.577400]   with arguments:
[   42.581780]     /init
[   42.584520]   with environment:
[   42.589320]     HOME=/
[   42.592140]     TERM=linux
[   42.637580] init[1]: unhandled signal 4 code 0x1 at 0x0000003f966980d8 in ld-linux-riscv64-lp64d.so.1[3f96683000+23000]
[   42.650580] CPU: 0 PID: 1 Comm: init Not tainted 6.1.62 #1-NixOS
[   42.657720] Hardware name: Barcelona Supercomputing Center - Lagarto Ox (NixOS) (DT)
[   42.666760] epc : 0000003f966980d8 ra : 0000000000000000 sp : 0000003fe5c95db0
[   42.675040]  gp : ffffffff8197ea48 tp : 0000000000000000 t0 : 0000000000000000
[   42.683320]  t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000000000000000
[   42.691600]  s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000
[   42.699880]  a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
[   42.708160]  a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000
[   42.716420]  s2 : 0000000000000000 s3 : 0000000000000000 s4 : 0000000000000000
[   42.724700]  s5 : 0000000000000000 s6 : 0000000000000000 s7 : 0000000000000000
[   42.733380]  s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[   42.741660]  s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000
[   42.749920]  t5 : 0000000000000000 t6 : 0000000000000000
[   42.756440] status: 0000000200004020 badaddr: 0000000000010513 cause: 0000000000000002
[   42.767620] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004
[   42.775720] CPU: 0 PID: 1 Comm: init Not tainted 6.1.62 #1-NixOS
[   42.782320] Hardware name: Barcelona Supercomputing Center - Lagarto Ox (NixOS) (DT)
[   42.790460] Call Trace:
[   42.793380] [<ffffffff800070c4>] dump_backtrace+0x38/0x48
[   42.799520] [<ffffffff809f063c>] show_stack+0x50/0x68
[   42.805280] [<ffffffff809fd1f8>] dump_stack_lvl+0x60/0x84
[   42.811400] [<ffffffff809fd23c>] dump_stack+0x20/0x30
[   42.817140] [<ffffffff809f0918>] panic+0x160/0x390
[   42.822620] [<ffffffff80020184>] do_exit+0xa70/0xa78
[   42.828260] [<ffffffff800203a4>] do_group_exit+0x44/0xb0
[   42.834240] [<ffffffff80031eec>] get_signal+0x9b4/0xa00
[   42.840140] [<ffffffff80005ca0>] do_work_pending+0x18c/0x610
[   42.846480] [<ffffffff80003880>] resume_userspace_slow+0x10/0x14
[   42.853420] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 ]---
2024-06-28 15:08:24 +02:00
fc4b8126f6 Document memory layout 2024-06-28 10:39:10 +02:00
a8f3234031 Reached working U-Boot prompt
The serial compatible string must be "ns16550" to be recognized by
U-Boot.
2024-06-27 17:58:21 +02:00
72b4788888 Reached U-Boot console with FDT parsing error 2024-06-27 16:08:30 +02:00
1bfc32e91a Working OpenSBI 1.2 2024-06-27 11:29:15 +02:00