Reached U-Boot console with FDT parsing error
This commit is contained in:
parent
1bfc32e91a
commit
72b4788888
@ -86,14 +86,30 @@
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};
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nixpkgs.overlays = [ (final: prev: {
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ox-dtb = prev.runCommand "ox.dtb" {
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nativeBuildInputs = [ prev.buildPackages.dtc ];
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} "dtc -O dtb -o $out ${./ox-plic.dts}";
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uboot = prev.ubootQemuRiscv64Smode.override {
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filesToInstall = [ "u-boot.bin" "u-boot-nodtb.bin" ];
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version = "2023.07.02-print-cpu-probe";
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src = builtins.fetchGit {
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url = "file:///home/Computational/rarias/riscv/u-boot";
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rev = "b0868e84c392daadcaf611f92209d0c82203386f";
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};
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#patches = [ ./u-boot-debug.patch ];
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extraConfig = ''
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CONFIG_RISCV_ISA_C=n
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CONFIG_REQUIRE_SERIAL_CONSOLE=n
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CONFIG_SERIAL_SEARCH_ALL=y
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CONFIG_SERIAL=y
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CONFIG_SERIAL_PUTS=y
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CONFIG_SHOW_BOOT_PROGRESS=y
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CONFIG_SHOW_REGS=y
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CONFIG_LIBCOMMON_SUPPORT=y
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CONFIG_SERIAL_SEARCH_ALL=n
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CONFIG_SERIAL_PROBE_ALL=n
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CONFIG_OF_CONTROL=y
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CONFIG_OF_BOARD=y
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CONFIG_OF_EMBED=y
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CONFIG_OF_HAS_PRIOR_STAGE=y
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CONFIG_BLKMAP=y
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CONFIG_CMD_BLKMAP=y
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@ -101,7 +117,18 @@
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_SBI_CONSOLE=y
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CONFIG_SYS_NS16550=n
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CONFIG_SMP=n
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CONFIG_TRACE_EARLY=y
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CONFIG_LOG=y
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CONFIG_LOGLEVEL=9
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CONFIG_LOG_MAX_LEVEL=9
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CONFIG_LOG_DEFAULT_LEVEL=9
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'';
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extraMakeFlags = [
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"KCPPFLAGS=-DLOG_DEBUG"
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#"EXT_DTB=${final.ox-dtb}"
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];
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};
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uboot-env = let
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@ -155,7 +182,7 @@
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#"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions
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#"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
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#"PLATFORM_RISCV_ABI=lp64d"
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"FW_PAYLOAD_PATH=${final.uboot}/u-boot-nodtb.bin"
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"FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin"
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"FW_FDT_PATH=ox.dtb"
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];
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patches = [ ./ox-alveo-platform-plic.patch ];
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229
ox-plic.dts
229
ox-plic.dts
@ -5,139 +5,138 @@
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox";
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chosen {
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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};
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cpus {
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x0000c350>;
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cpu@0 {
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clock-frequency = <0x02FAF080>;
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device_type = "cpu";
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reg = <0x00000000>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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L3: interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x0000c350>;
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cpu@0 {
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clock-frequency = <0x02FAF080>;
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device_type = "cpu";
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reg = <0x00000000>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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L3: interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
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};
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reserved-memory {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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ranges;
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eth_pool: dma_pool@60000000 {
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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};
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onic_pool: dma_pool@70000000 {
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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};
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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ranges;
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eth_pool: dma_pool@60000000 {
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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};
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onic_pool: dma_pool@70000000 {
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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};
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};
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eth0_clk: eth0_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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};
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pmem@1bff00000 {
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
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};
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pmem2@1b7f00000 {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
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};
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pmem3@f7e00000 {
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volatile;
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compatible = "pmem-region";
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reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
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volatile;
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compatible = "pmem-region";
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reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
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};
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soc {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "BSC,Lagarto-bare-soc", "simple-bus";
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ranges;
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serial@40001000 {
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compatible = "ns16750";
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reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
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interrupts = <0x00000000>;
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port-number = <0x00000000>;
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reg-shift = <0x00000002>;
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clock-frequency = <0x02FAF080>;
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current-speed = <0x0001c200>;
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status = "okay";
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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ranges;
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serial@40001000 {
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compatible = "ns16750";
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reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
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interrupts = <0x00000000>;
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port-number = <0x00000000>;
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reg-shift = <0x00000002>;
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clock-frequency = <0x02FAF080>;
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current-speed = <0x0001c200>;
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status = "okay";
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};
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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carv,mtu = <0x000005dc>;
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carv,no-mac;
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device_type = "network";
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local-mac-address = [02 05 00 01 00 05];
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axistream-connected = <0x000000fe>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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};
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dma@40400000 {
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xlnx,include-dre;
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phandle = <0x000000fe>;
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#dma-cells = <0x00000001>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>;
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reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <&PLIC0>;
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interrupts = <0x00000002 0x00000003>;
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xlnx,addrwidth = <0x00000028>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x00000017>;
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dma-channel@40400000 {
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0x00000000>;
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interrupts = <0x00000002>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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carv,mtu = <0x000005dc>;
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carv,no-mac;
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device_type = "network";
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local-mac-address = [02 05 00 01 00 05];
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axistream-connected = <0x000000fe>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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};
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dma@40400000 {
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xlnx,include-dre;
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phandle = <0x000000fe>;
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#dma-cells = <0x00000001>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>;
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reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <&PLIC0>;
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interrupts = <0x00000002 0x00000003>;
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xlnx,addrwidth = <0x00000028>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x00000017>;
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dma-channel@40400000 {
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0x00000000>;
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interrupts = <0x00000002>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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dma-channel@40400030 {
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <0x00000001>;
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interrupts = <0x00000003>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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};
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clint@40002000 {
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reg-names = "control";
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interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
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compatible = "riscv,clint0";
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#interrupt-cells = <0x00000001>;
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reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
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};
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PLIC0: plic@40800000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L3 3 &L3 7>;
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reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
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riscv,ndev = <0x00000003>;
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riscv,max-priority = <0x00000007>;
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dma-channel@40400030 {
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <0x00000001>;
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interrupts = <0x00000003>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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};
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clint@40002000 {
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reg-names = "control";
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interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
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compatible = "riscv,clint0";
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#interrupt-cells = <0x00000001>;
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reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
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};
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PLIC0: plic@40800000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L3 3 &L3 7>;
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reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
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riscv,ndev = <0x00000003>;
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riscv,max-priority = <0x00000007>;
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};
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};
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};
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2
ox.dts
2
ox.dts
@ -35,7 +35,7 @@
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uart0: serial@40001000 {
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compatible = "ns16750";
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//reg = <0x40001000 0x1000>;
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reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
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reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
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interrupts = <0>;
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port-number = <0>;
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reg-shift = <2>;
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83
u-boot-debug.patch
Normal file
83
u-boot-debug.patch
Normal file
@ -0,0 +1,83 @@
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diff --git a/common/board_f.c b/common/board_f.c
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index 1688e27071..216839febb 100644
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--- a/common/board_f.c
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+++ b/common/board_f.c
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@@ -978,6 +978,8 @@ static const init_fnc_t init_sequence_f[] = {
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void board_init_f(ulong boot_flags)
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{
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+ puts("board_init_f() called\n");
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+
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gd->flags = boot_flags;
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gd->have_console = 0;
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@@ -990,6 +992,7 @@ void board_init_f(ulong boot_flags)
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/* NOTREACHED - jump_to_copy() does not return */
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hang();
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#endif
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+ puts("board_init_f() ends ok\n");
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}
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#if defined(CONFIG_X86) || defined(CONFIG_ARC)
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diff --git a/common/board_r.c b/common/board_r.c
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index d798c00a80..cb8119a603 100644
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--- a/common/board_r.c
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+++ b/common/board_r.c
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@@ -786,6 +786,8 @@ static init_fnc_t init_sequence_r[] = {
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void board_init_r(gd_t *new_gd, ulong dest_addr)
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{
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+ puts("board_init_r called\n");
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+
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/*
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* The pre-relocation drivers may be using memory that has now gone
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* away. Mark serial as unavailable - this will fall back to the debug
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diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
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index d6484d7f4b..64a507248d 100644
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--- a/drivers/cpu/riscv_cpu.c
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+++ b/drivers/cpu/riscv_cpu.c
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@@ -92,10 +92,13 @@ static int riscv_cpu_get_count(const struct udevice *dev)
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static int riscv_cpu_bind(struct udevice *dev)
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{
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+ puts("riscv_cpu_bind called()\n");
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+
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struct cpu_plat *plat = dev_get_parent_plat(dev);
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struct driver *drv;
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int ret;
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+ puts("looking for timebase-frequency\n");
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/* save the hart id */
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plat->cpu_id = dev_read_addr(dev);
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/* first examine the property in current cpu node */
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@@ -105,6 +108,8 @@ static int riscv_cpu_bind(struct udevice *dev)
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dev_read_u32(dev->parent, "timebase-frequency",
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&plat->timebase_freq);
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+ printf("timebase-frequency=%lu\n", (unsigned long) plat->timebase_freq);
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+
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/*
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* Bind riscv-timer driver on boot hart.
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*
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@@ -125,6 +130,8 @@ static int riscv_cpu_bind(struct udevice *dev)
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device_bind_with_driver_data(dev, drv, "riscv_timer",
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plat->timebase_freq, ofnode_null(),
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NULL);
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+ } else {
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+ printf("ignoring cpu_id=%d\n", plat->cpu_id);
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}
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return 0;
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diff --git a/lib/hang.c b/lib/hang.c
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index 2735774f9a..84eff21ffc 100644
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--- a/lib/hang.c
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+++ b/lib/hang.c
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@@ -22,6 +22,8 @@
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*/
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void hang(void)
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{
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+ puts("oh no, we are in hang()\n");
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+
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#if !defined(CONFIG_SPL_BUILD) || \
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(CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \
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CONFIG_IS_ENABLED(SERIAL))
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278
xavi-good-ftd.dts
Normal file
278
xavi-good-ftd.dts
Normal file
@ -0,0 +1,278 @@
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LOx$
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OpenSBI v1.2
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____ _____ ____ _____
|
||||
/ __ \ / ____| _ \_ _|
|
||||
| | | |_ __ ___ _ __ | (___ | |_) || |
|
||||
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
|
||||
| |__| | |_) | __/ | | |____) | |_) || |_
|
||||
\____/| .__/ \___|_| |_|_____/|____/_____|
|
||||
| |
|
||||
|_|
|
||||
|
||||
Platform Name : Sargantana (for Xilinx Alveo FPGA)
|
||||
Platform Features : medeleg
|
||||
Platform HART Count : 1
|
||||
Platform IPI Device : ---
|
||||
Platform Timer Device : generic_timer @ 25000000Hz
|
||||
Platform Console Device : alveo_uart
|
||||
Platform HSM Device : ---
|
||||
Platform PMU Device : ---
|
||||
Platform Reboot Device : ---
|
||||
Platform Shutdown Device : ---
|
||||
Firmware Base : 0x80000000
|
||||
Firmware Size : 148 KB
|
||||
Runtime SBI Version : 1.0
|
||||
|
||||
Domain0 Name : root
|
||||
Domain0 Boot HART : 0
|
||||
Domain0 HARTs : 0*
|
||||
Domain0 Region00 : 0x0000000080000000-0x000000008003ffff ()
|
||||
Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
|
||||
Domain0 Next Address : 0x0000000080200000
|
||||
Domain0 Next Arg1 : 0x0000000080010000
|
||||
Domain0 Next Mode : S-mode
|
||||
Domain0 SysReset : yes
|
||||
|
||||
Boot HART ID : 0
|
||||
Boot HART Domain : root
|
||||
Boot HART Priv Version : v1.10
|
||||
Boot HART Base ISA : rv64imafdc
|
||||
Boot HART ISA Extensions : time
|
||||
Boot HART PMP Count : 0
|
||||
Boot HART PMP Granularity : 0
|
||||
Boot HART PMP Address Bits: 0
|
||||
Boot HART MHPM Count : 29
|
||||
Boot HART MIDELEG : 0x0000000000000222
|
||||
Boot HART MEDELEG : 0x000000000000b109
|
||||
|
||||
<debug_uart>
|
||||
Core: 9 devices, 8 uclasses, devicetree: separate
|
||||
MMC:
|
||||
Loading Environment from <NULL>... OK
|
||||
In: serial@40001000
|
||||
Out: serial@40001000
|
||||
Err: serial@40001000
|
||||
Model: Barcelona Supercomputing Center - Lagarto Ox
|
||||
Hit any key to stop autoboot: 0
|
||||
LOx$ fdt
|
||||
fdt - flattened device tree utility commands
|
||||
|
||||
Usage:
|
||||
fdt addr [-c] [-q] <addr> [<size>] - Set the [control] fdt location to <addr>
|
||||
fdt apply <addr> - Apply overlay to the DT
|
||||
fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active
|
||||
fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed
|
||||
fdt print <path> [<prop>] - Recursive print starting at <path>
|
||||
fdt list <path> [<prop>] - Print one level starting at <path>
|
||||
fdt get value <var> <path> <prop> [<index>] - Get <property> and store in <var>
|
||||
In case of stringlist property, use optional <index>
|
||||
to select string within the stringlist. Default is 0.
|
||||
fdt get name <var> <path> <index> - Get name of node <index> and store in <var>
|
||||
fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var>
|
||||
fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var>
|
||||
fdt set <path> <prop> [<val>] - Set <property> [to <val>]
|
||||
fdt mknode <path> <node> - Create a new node after <path>
|
||||
fdt rm <path> [<prop>] - Delete the node or <property>
|
||||
fdt header [get <var> <member>] - Display header info
|
||||
get - get header member <member> and store it in <var>
|
||||
fdt bootcpu <id> - Set boot cpuid
|
||||
fdt memory <addr> <size> - Add/Update memory node
|
||||
fdt rsvmem print - Show current mem reserves
|
||||
fdt rsvmem add <addr> <size> - Add a mem reserve
|
||||
fdt rsvmem delete <index> - Delete a mem reserves
|
||||
fdt chosen [<start> <size>] - Add/update the /chosen branch in the tree
|
||||
<start>/<size> - initrd start addr/size
|
||||
NOTE: Dereference aliases by omitting the leading '/', e.g. fdt print ethernet0.
|
||||
LOx$ fdt print
|
||||
No FDT memory address configured. Please configure
|
||||
the FDT address via "fdt addr <address>" command.
|
||||
Aborting!
|
||||
LOx$ fdt list
|
||||
No FDT memory address configured. Please configure
|
||||
the FDT address via "fdt addr <address>" command.
|
||||
Aborting!
|
||||
LOx$ printenv
|
||||
arch=riscv
|
||||
baudrate=115200
|
||||
board=riscv64
|
||||
board_name=riscv64
|
||||
bootcmd=fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; blkmap create pmem2; blkmap map pmem2 0 0x40000 mem 0x1b7f00000; blkmap info; ls blkmap 0; load blkmap 0 ${kernel_addr_r} Image; setenv bootargs ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash; booti ${kernel_addr_r} - ${fdt_addr_r};
|
||||
bootdelay=10
|
||||
cpu=generic
|
||||
fdt_addr_r=0x86000000
|
||||
fdtcontroladdr=e7d87e60
|
||||
image=boot/Image
|
||||
kernel_addr_r=0x80200000
|
||||
loadaddr=0x87000000
|
||||
mmcdev=0
|
||||
mmcpart=1
|
||||
stderr=serial@40001000
|
||||
stdin=serial@40001000
|
||||
stdout=serial@40001000
|
||||
vendor=openpiton
|
||||
|
||||
Environment size: 640/126972 bytes
|
||||
LOx$ fdt addr ${fdt_addr_r}
|
||||
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
|
||||
LOx$ fdt addr ${fdtcontroladdr}
|
||||
Working FDT set to e7d87e60
|
||||
LOx$ fdt print
|
||||
/ {
|
||||
#address-cells = <0x00000002>;
|
||||
#size-cells = <0x00000002>;
|
||||
compatible = "riscv,rv64i";
|
||||
model = "Barcelona Supercomputing Center - Lagarto Ox";
|
||||
chosen {
|
||||
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
|
||||
};
|
||||
cpus {
|
||||
#address-cells = <0x00000001>;
|
||||
#size-cells = <0x00000000>;
|
||||
timebase-frequency = <0x0000c350>;
|
||||
cpu@0 {
|
||||
clock-frequency = <0x02faf080>;
|
||||
device_type = "cpu";
|
||||
reg = <0x00000000>;
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "rv64imafd";
|
||||
mmu-type = "riscv,sv39";
|
||||
tlb-split;
|
||||
phandle = <0x00000004>;
|
||||
interrupt-controller {
|
||||
#interrupt-cells = <0x00000001>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
phandle = <0x00000005>;
|
||||
};
|
||||
};
|
||||
};
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
|
||||
};
|
||||
reserved-memory {
|
||||
#address-cells = <0x00000002>;
|
||||
#size-cells = <0x00000002>;
|
||||
ranges;
|
||||
dma_pool@60000000 {
|
||||
reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
phandle = <0x00000001>;
|
||||
};
|
||||
dma_pool@70000000 {
|
||||
reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
phandle = <0x00000006>;
|
||||
};
|
||||
};
|
||||
eth0_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x00000000>;
|
||||
clock-frequency = <0x09502f90>;
|
||||
phandle = <0x00000002>;
|
||||
};
|
||||
pmem@1bff00000 {
|
||||
volatile;
|
||||
compatible = "pmem-region";
|
||||
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
|
||||
};
|
||||
pmem2@1b7f00000 {
|
||||
#address-cells = <0x00000002>;
|
||||
#size-cells = <0x00000002>;
|
||||
volatile;
|
||||
compatible = "pmem-region";
|
||||
reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
|
||||
};
|
||||
pmem3@f7e00000 {
|
||||
volatile;
|
||||
compatible = "pmem-region";
|
||||
reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
|
||||
};
|
||||
soc {
|
||||
#address-cells = <0x00000002>;
|
||||
#size-cells = <0x00000002>;
|
||||
compatible = "BSC,Lagarto-bare-soc", "simple-bus";
|
||||
ranges;
|
||||
serial@40001000 {
|
||||
compatible = "ns16750";
|
||||
reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
|
||||
interrupts = <0x00000000>;
|
||||
port-number = <0x00000000>;
|
||||
reg-shift = <0x00000002>;
|
||||
clock-frequency = <0x017d7840>;
|
||||
current-speed = <0x0001c200>;
|
||||
status = "okay";
|
||||
phandle = <0x00000007>;
|
||||
};
|
||||
ethernet0 {
|
||||
xlnx,rxmem = <0x000005f2>;
|
||||
carv,mtu = <0x000005dc>;
|
||||
carv,no-mac;
|
||||
device_type = "network";
|
||||
local-mac-address = [02 05 00 01 00 05];
|
||||
axistream-connected = <0x000000fe>;
|
||||
compatible = "xlnx,xxv-ethernet-1.0-carv";
|
||||
memory-region = <0x00000001>;
|
||||
};
|
||||
dma@40020000 {
|
||||
xlnx,include-dre;
|
||||
phandle = <0x000000fe>;
|
||||
#dma-cells = <0x00000001>;
|
||||
compatible = "xlnx,axi-dma-1.00.a";
|
||||
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
|
||||
clocks = <0x00000002 0x00000002 0x00000002 0x00000002>;
|
||||
reg = <0x00000000 0x40200000 0x00000000 0x00400000>;
|
||||
interrupt-names = "mm2s_introut", "s2mm_introut";
|
||||
interrupt-parent = <0x00000003>;
|
||||
interrupts = <0x00000002 0x00000003>;
|
||||
xlnx,addrwidth = <0x00000028>;
|
||||
xlnx,include-sg;
|
||||
xlnx,sg-length-width = <0x00000017>;
|
||||
dma-channel@40020000 {
|
||||
compatible = "xlnx,axi-dma-mm2s-channel";
|
||||
dma-channels = <0x00000001>;
|
||||
interrupts = <0x00000002>;
|
||||
xlnx,datawidth = <0x00000040>;
|
||||
xlnx,device-id = <0x00000000>;
|
||||
xlnx,include-dre;
|
||||
};
|
||||
dma-channel@40020030 {
|
||||
compatible = "xlnx,axi-dma-s2mm-channel";
|
||||
dma-channels = <0x00000001>;
|
||||
interrupts = <0x00000003>;
|
||||
xlnx,datawidth = <0x00000040>;
|
||||
xlnx,device-id = <0x00000000>;
|
||||
xlnx,include-dre;
|
||||
};
|
||||
};
|
||||
clint@40002000 {
|
||||
reg-names = "control";
|
||||
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
|
||||
compatible = "riscv,clint0";
|
||||
#interrupt-cells = <0x00000001>;
|
||||
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
|
||||
};
|
||||
plic@fff1100000 {
|
||||
#address-cells = <0x00000000>;
|
||||
compatible = "riscv,plic0";
|
||||
#interrupt-cells = <0x00000001>;
|
||||
reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
|
||||
riscv,ndev = <0x00000003>;
|
||||
riscv,max-priority = <0x00000007>;
|
||||
interrupt-controller;
|
||||
phandle = <0x00000003>;
|
||||
};
|
||||
};
|
||||
__symbols__ {
|
||||
CPU0 = "/cpus/cpu@0";
|
||||
CPU0_intc = "/cpus/cpu@0/interrupt-controller";
|
||||
eth_pool = "/reserved-memory/dma_pool@60000000";
|
||||
meep_pool = "/reserved-memory/dma_pool@70000000";
|
||||
eth0_clk = "/eth0_clk";
|
||||
uart0 = "/soc/serial@40001000";
|
||||
dma_eth = "/soc/dma@40020000";
|
||||
PLIC0 = "/soc/plic@fff1100000";
|
||||
};
|
||||
};
|
||||
LOx$
|
||||
Loading…
Reference in New Issue
Block a user