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nixos-riscv/xavi-good-ftd.dts

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LOx$
OpenSBI v1.2
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| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
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\____/| .__/ \___|_| |_|_____/|____/_____|
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Platform Name : Sargantana (for Xilinx Alveo FPGA)
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : ---
Platform Timer Device : generic_timer @ 25000000Hz
Platform Console Device : alveo_uart
Platform HSM Device : ---
Platform PMU Device : ---
Platform Reboot Device : ---
Platform Shutdown Device : ---
Firmware Base : 0x80000000
Firmware Size : 148 KB
Runtime SBI Version : 1.0
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x0000000080010000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART Priv Version : v1.10
Boot HART Base ISA : rv64imafdc
Boot HART ISA Extensions : time
Boot HART PMP Count : 0
Boot HART PMP Granularity : 0
Boot HART PMP Address Bits: 0
Boot HART MHPM Count : 29
Boot HART MIDELEG : 0x0000000000000222
Boot HART MEDELEG : 0x000000000000b109
<debug_uart>
Core: 9 devices, 8 uclasses, devicetree: separate
MMC:
Loading Environment from <NULL>... OK
In: serial@40001000
Out: serial@40001000
Err: serial@40001000
Model: Barcelona Supercomputing Center - Lagarto Ox
Hit any key to stop autoboot: 0
LOx$ fdt
fdt - flattened device tree utility commands
Usage:
fdt addr [-c] [-q] <addr> [<size>] - Set the [control] fdt location to <addr>
fdt apply <addr> - Apply overlay to the DT
fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active
fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed
fdt print <path> [<prop>] - Recursive print starting at <path>
fdt list <path> [<prop>] - Print one level starting at <path>
fdt get value <var> <path> <prop> [<index>] - Get <property> and store in <var>
In case of stringlist property, use optional <index>
to select string within the stringlist. Default is 0.
fdt get name <var> <path> <index> - Get name of node <index> and store in <var>
fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var>
fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var>
fdt set <path> <prop> [<val>] - Set <property> [to <val>]
fdt mknode <path> <node> - Create a new node after <path>
fdt rm <path> [<prop>] - Delete the node or <property>
fdt header [get <var> <member>] - Display header info
get - get header member <member> and store it in <var>
fdt bootcpu <id> - Set boot cpuid
fdt memory <addr> <size> - Add/Update memory node
fdt rsvmem print - Show current mem reserves
fdt rsvmem add <addr> <size> - Add a mem reserve
fdt rsvmem delete <index> - Delete a mem reserves
fdt chosen [<start> <size>] - Add/update the /chosen branch in the tree
<start>/<size> - initrd start addr/size
NOTE: Dereference aliases by omitting the leading '/', e.g. fdt print ethernet0.
LOx$ fdt print
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
LOx$ fdt list
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
LOx$ printenv
arch=riscv
baudrate=115200
board=riscv64
board_name=riscv64
bootcmd=fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; blkmap create pmem2; blkmap map pmem2 0 0x40000 mem 0x1b7f00000; blkmap info; ls blkmap 0; load blkmap 0 ${kernel_addr_r} Image; setenv bootargs ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash; booti ${kernel_addr_r} - ${fdt_addr_r};
bootdelay=10
cpu=generic
fdt_addr_r=0x86000000
fdtcontroladdr=e7d87e60
image=boot/Image
kernel_addr_r=0x80200000
loadaddr=0x87000000
mmcdev=0
mmcpart=1
stderr=serial@40001000
stdin=serial@40001000
stdout=serial@40001000
vendor=openpiton
Environment size: 640/126972 bytes
LOx$ fdt addr ${fdt_addr_r}
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
LOx$ fdt addr ${fdtcontroladdr}
Working FDT set to e7d87e60
LOx$ fdt print
/ {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "riscv,rv64i";
model = "Barcelona Supercomputing Center - Lagarto Ox";
chosen {
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
};
cpus {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
timebase-frequency = <0x0000c350>;
cpu@0 {
clock-frequency = <0x02faf080>;
device_type = "cpu";
reg = <0x00000000>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafd";
mmu-type = "riscv,sv39";
tlb-split;
phandle = <0x00000004>;
interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x00000005>;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
};
reserved-memory {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
dma_pool@60000000 {
reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool";
phandle = <0x00000001>;
};
dma_pool@70000000 {
reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool";
phandle = <0x00000006>;
};
};
eth0_clk {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x09502f90>;
phandle = <0x00000002>;
};
pmem@1bff00000 {
volatile;
compatible = "pmem-region";
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
};
pmem2@1b7f00000 {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
volatile;
compatible = "pmem-region";
reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
};
pmem3@f7e00000 {
volatile;
compatible = "pmem-region";
reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
};
soc {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "BSC,Lagarto-bare-soc", "simple-bus";
ranges;
serial@40001000 {
compatible = "ns16750";
reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
interrupts = <0x00000000>;
port-number = <0x00000000>;
reg-shift = <0x00000002>;
clock-frequency = <0x017d7840>;
current-speed = <0x0001c200>;
status = "okay";
phandle = <0x00000007>;
};
ethernet0 {
xlnx,rxmem = <0x000005f2>;
carv,mtu = <0x000005dc>;
carv,no-mac;
device_type = "network";
local-mac-address = [02 05 00 01 00 05];
axistream-connected = <0x000000fe>;
compatible = "xlnx,xxv-ethernet-1.0-carv";
memory-region = <0x00000001>;
};
dma@40020000 {
xlnx,include-dre;
phandle = <0x000000fe>;
#dma-cells = <0x00000001>;
compatible = "xlnx,axi-dma-1.00.a";
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <0x00000002 0x00000002 0x00000002 0x00000002>;
reg = <0x00000000 0x40200000 0x00000000 0x00400000>;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <0x00000003>;
interrupts = <0x00000002 0x00000003>;
xlnx,addrwidth = <0x00000028>;
xlnx,include-sg;
xlnx,sg-length-width = <0x00000017>;
dma-channel@40020000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000002>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
dma-channel@40020030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000003>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
};
clint@40002000 {
reg-names = "control";
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
compatible = "riscv,clint0";
#interrupt-cells = <0x00000001>;
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
};
plic@fff1100000 {
#address-cells = <0x00000000>;
compatible = "riscv,plic0";
#interrupt-cells = <0x00000001>;
reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
riscv,ndev = <0x00000003>;
riscv,max-priority = <0x00000007>;
interrupt-controller;
phandle = <0x00000003>;
};
};
__symbols__ {
CPU0 = "/cpus/cpu@0";
CPU0_intc = "/cpus/cpu@0/interrupt-controller";
eth_pool = "/reserved-memory/dma_pool@60000000";
meep_pool = "/reserved-memory/dma_pool@70000000";
eth0_clk = "/eth0_clk";
uart0 = "/soc/serial@40001000";
dma_eth = "/soc/dma@40020000";
PLIC0 = "/soc/plic@fff1100000";
};
};
LOx$
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