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Try setting the mtimecmp address

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Rodrigo Arias 2024-07-12 14:14:25 +02:00
parent 6a57dd004f
commit 8b2821f2f2
2 changed files with 42 additions and 1 deletions
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40
JOURNAL.md
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@ -1712,3 +1712,43 @@ typos in the printf command, this is the patch:
So, let's fix the patch and switch to the "riscv,aclint-mtimer" timer, which
doesn't set any quirk or weird offset.
GGGGGGGGG
OpenSBI v1.5
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
sbi_timer_init: begins
sbi_timer_init: got Zicntr extension
fdt_timer_cold_init: pos = 0
fdt_timer_cold_init: got match, name = riscv,aclint-mtimer
fdt_timer_cold_init: enabled
timer_mtimer_cold_init: begins, is_clint = 0
timer_mtimer_cold_init: mtime_addr = 0x40002000
timer_mtimer_cold_init: mtime_size = 0x000c0000
timer_mtimer_cold_init: mtimecmp_addr = 0x00000000
timer_mtimer_cold_init: mtimecmp_size = 0x00000000
fdt_timer_cold_init: drc->cold_init = -3
fdt_timer_init: fdt_timer_cold_init failed (-3)
sbi_platform_timer: sbi_platform_timer_init failed (-3)
init_coldboot: timer init failed (error -3)
So, now we have better addresses, but this is not what I would expect. The regs
property is being used to set the mtime address and size, while I would expect
it to set the `mtimecmp_addr` too, but it seems it is expecting two pairs of
address and size in the regs:
reg = <0x0 0x40002000 0x0 0x000c0000>;
So, first let's add the mtimecmp after the mtime registers and see if that
clears the -3 error.
I'll leave it at 0x40002000, but I suspect the address might be 0x40170000:
#define OX_ALVEO_TIMER_BASE 0x40170000

3
ox-plic.dts
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@ -229,7 +229,8 @@
* Documentation/devicetree/bindings/riscv/cpus.yaml
*/
clint: clint@40002000 {
reg = <0x0 0x40002000 0x0 0x000c0000>;
/* MTIME and MTIMECMP address and size pairs */
reg = <0x0 0x40002000 0x0 0x8>, <0x0 0x40002008 0x0 0x8>;
interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
/*<&CPU0 0x3>, <&CPU0 0x7>,*/
/*<&onic_pool 0x3>, <&onic_pool 0x7>,*/