Simplify, correct and comment DTS
Disable unused devices and try to fix the interrupt connections. The compiler dtc doesn't report any warning now.
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33b227f576
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763f053f01
198
ox-plic.dts
198
ox-plic.dts
@ -1,31 +1,42 @@
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/dts-v1/;
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/ {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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#address-cells = <2>;
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#size-cells = <2>; /* 64 bits memory addresses */
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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chosen {
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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};
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cpus {
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x0000c350>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Timer */
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timebase-frequency = <50000>; /* 50 kHz */
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CPU0: cpu@0 {
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clock-frequency = <0x02FAF080>;
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clock-frequency = <50000000>; /* 50 MHz */
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device_type = "cpu";
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reg = <0x00000000>;
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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phandle = <0x00000004>;
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L3: interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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/* Hart-Level Interrupt Controller: Every interrupt is
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* ultimately routed through a hart's HLIC before it
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* interrupts that hart. */
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HLIC0: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller; /* Receives interrupts */
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compatible = "riscv,cpu-intc";
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phandle = <0x00000005>;
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phandle = <0x5>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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};
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};
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};
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@ -39,29 +50,27 @@
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*/
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x7ff00000>;
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reg = <0x0 0x80000000 0x0 0x7ff00000>;
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};
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reserved-memory {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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#address-cells = <2>; /* Starting address and size */
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#size-cells = <2>; /* 64 bits memory addresses */
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ranges;
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eth_pool: dma_pool@60000000 {
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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reg = <0x0 0x60000000 0x0 0x10000000>;
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compatible = "shared-dma-pool";
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phandle = <0x00000001>;
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};
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onic_pool: dma_pool@70000000 {
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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reg = <0x0 0x70000000 0x0 0x10000000>;
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compatible = "shared-dma-pool";
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phandle = <0x00000006>;
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};
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};
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eth0_clk: eth0_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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phandle = <0x00000002>;
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};
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// eth0_clk: eth0_clk {
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// compatible = "fixed-clock";
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// #clock-cells = <0x00000000>;
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// clock-frequency = <0x09502f90>;
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// phandle = <0x00000002>;
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// };
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pmem@1bff00000 {
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/* volatile; This property indicates that this region is
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* actually backed by non-persistent memory. This lets the OS
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@ -69,7 +78,7 @@
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* data is made persistent after a write. */
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
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reg = <0x1 0xbff00000 0x0 0xc0100000>;
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};
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soc {
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#address-cells = <0x00000002>;
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@ -78,76 +87,87 @@
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ranges;
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SERIAL: serial@40001000 {
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compatible = "ns16550";
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reg = <0x0 0x40001000 0x0 0x00000100>;
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interrupts = <0>;
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/*port-number = <0>;*/
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reg = <0x0 0x40001000 0x0 0x100>;
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interrupts = <0>; /* Output interrupt 0 */
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interrupt-parent = <&PLIC>;
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reg-shift = <2>;
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clock-frequency = <50000000>;
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current-speed = <115200>;
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status = "okay";
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phandle = <0x00000007>;
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};
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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carv,mtu = <0x000005dc>;
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carv,no-mac;
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device_type = "network";
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local-mac-address = [02 05 00 01 00 05];
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axistream-connected = <0x000000fe>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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};
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dma@40400000 {
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xlnx,include-dre;
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phandle = <0x000000fe>;
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#dma-cells = <0x00000001>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>;
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reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <&PLIC0>;
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interrupts = <0x00000002 0x00000003>;
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xlnx,addrwidth = <0x00000028>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x00000017>;
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dma-channel@40400000 {
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0x00000000>;
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interrupts = <0x00000002>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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dma-channel@40400030 {
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <0x00000001>;
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interrupts = <0x00000003>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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};
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clint@40002000 {
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reg-names = "control";
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interrupts-extended =
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<&CPU0 0x3>, <&CPU0 0x7>,
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<&L3 0x3>, <&L3 0x7>,
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<&onic_pool 0x3>, <&onic_pool 0x7>,
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<&SERIAL 0x3>, <&SERIAL 0x7>;
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compatible = "riscv,clint0";
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#interrupt-cells = <0x00000001>;
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reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
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};
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PLIC0: plic@40800000 {
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#interrupt-cells = <1>;
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// ethernet0 {
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// xlnx,rxmem = <0x000005f2>;
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// carv,mtu = <0x000005dc>;
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// carv,no-mac;
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// device_type = "network";
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// local-mac-address = [02 05 00 01 00 05];
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// axistream-connected = <0x000000fe>;
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// compatible = "xlnx,xxv-ethernet-1.0-carv";
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// memory-region = <ð_pool>;
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// };
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// dma@40400000 {
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// xlnx,include-dre;
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// phandle = <0x000000fe>;
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// #dma-cells = <0x00000001>;
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// compatible = "xlnx,axi-dma-1.00.a";
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// clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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// clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>;
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// reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
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// interrupt-names = "mm2s_introut", "s2mm_introut";
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// interrupt-parent = <&PLIC>;
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// interrupts = <2 3>;
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// xlnx,addrwidth = <0x00000028>;
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// xlnx,include-sg;
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// xlnx,sg-length-width = <0x00000017>;
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// dma-channel@40400000 {
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// compatible = "xlnx,axi-dma-mm2s-channel";
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// dma-channels = <0x00000000>;
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// interrupts = <0x00000002>;
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// xlnx,datawidth = <0x00000040>;
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// xlnx,device-id = <0x00000000>;
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// xlnx,include-dre;
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// };
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// dma-channel@40400030 {
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// compatible = "xlnx,axi-dma-s2mm-channel";
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// dma-channels = <0x00000001>;
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// interrupts = <0x00000003>;
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// xlnx,datawidth = <0x00000040>;
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// xlnx,device-id = <0x00000000>;
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// xlnx,include-dre;
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// };
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// };
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/* Platform-Level Interrupt Controller: Delivers interrupts to
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* HARTs. */
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PLIC: plic@40800000 {
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L3 3 &L3 7>;
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reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
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riscv,ndev = <0x00000003>;
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riscv,max-priority = <0x00000007>;
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phandle = <0x00000003>;
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interrupt-controller; /* Receives interrupts */
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#interrupt-cells = <1>;
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/* Sends interrupts to HART interrupt controllers */
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interrupts-extended = <&HLIC0 3 &HLIC0 7>;
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reg = < 0x0 0x40800000 0x0 0x00400000>;
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riscv,ndev = <0x3>;
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riscv,max-priority = <0x7>;
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phandle = <0x3>;
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};
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/* Core Local Interruptor: It directly connects to the timer and
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* inter-processor interrupt lines of various HARTs (or CPUs) so
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* RISC-V per-HART (or per-CPU) local interrupt controller is
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* the parent interrupt controller for CLINT device. The clock
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* frequency of CLINT is specified via "timebase-frequency" DT
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* property of "/cpus" DT node. The "timebase-frequency" DT
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* property is described in
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* Documentation/devicetree/bindings/riscv/cpus.yaml
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*/
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timer@40002000 {
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reg = <0x0 0x40002000 0x0 0x000c0000>;
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reg-names = "control";
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interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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/*<&CPU0 0x3>, <&CPU0 0x7>,*/
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/*<&onic_pool 0x3>, <&onic_pool 0x7>,*/
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/*<&SERIAL 0x3>, <&SERIAL 0x7>*/
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compatible = "riscv,clint0";
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};
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};
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};
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