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Extend the serial range from 0x100 to 0x1000

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The AXI UART 16550 v2.0 from Xilinx only seem to require 32 bytes for
the registes, but let's reduce the changes with the original DTS.
This commit is contained in:
Rodrigo Arias 2024-07-04 16:47:56 +02:00
parent d5b5cc3363
commit fcf4977a65
1 changed files with 1 additions and 1 deletions
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2
ox-plic.dts
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@ -88,7 +88,7 @@
ranges;
SERIAL: serial@40001000 {
compatible = "ns16550";
reg = <0x0 0x40001000 0x0 0x100>;
reg = <0x0 0x40001000 0x0 0x1000>;
interrupts = <1>; /* Output interrupt 1 */
interrupt-parent = <&PLIC>;
reg-shift = <2>;