From fcf4977a65a7b71c5aaaa4932d16f8c98318035f Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
Date: Thu, 4 Jul 2024 16:47:56 +0200
Subject: [PATCH] Extend the serial range from 0x100 to 0x1000

The AXI UART 16550 v2.0 from Xilinx only seem to require 32 bytes for
the registes, but let's reduce the changes with the original DTS.
---
 ox-plic.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ox-plic.dts b/ox-plic.dts
index af572d7..439e34b 100644
--- a/ox-plic.dts
+++ b/ox-plic.dts
@@ -88,7 +88,7 @@
 		ranges;
 		SERIAL: serial@40001000 {
 			compatible = "ns16550";
-			reg = <0x0 0x40001000 0x0 0x100>;
+			reg = <0x0 0x40001000 0x0 0x1000>;
 			interrupts = <1>; /* Output interrupt 1 */
 			interrupt-parent = <&PLIC>;
 			reg-shift = <2>;