nixos-riscv/dts/lagarto_ox.dts

#include "lagarto_ox.h"

/dts-v1/;
/ {
	#address-cells = <2>;
	#size-cells = <2>; /* 64 bits memory addresses */
	compatible = "riscv,rv64i";
	model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";

	aliases {
		serial0 = &uart_console; // ttyS0
//		serial1 = &uart_testing; // ttyS1
	};

//	chosen {
//		bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
//	};
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		timebase-frequency = <RTC_CLOCK_FREQUENCY>;
		CPU0: cpu@0 {
			clock-frequency = <CPU_CLOCK_FREQUENCY>;
			device_type = "cpu";
			reg = <0>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafd";
			mmu-type = "riscv,sv39";
			tlb-split;

			// OpenPiton+Ariane Platform
			// L1I Size / Assoc:   16 kB / 4
			// L1D Size / Assoc:   32 kB / 4
			// L15 Size / Assoc:  128 kB / 8
			// L2  Size / Assoc:  256 kB / 4
			// L15/L1D Cacheline size 64

			i-cache-block-size = <64>; // Guess
			i-cache-sets = <4>;
			i-cache-size = <16384>;
			i-tlb-sets = <1>; // Guess
			i-tlb-size = <32>; // Guess

			d-cache-block-size = <64>; // Guess
			d-cache-sets = <4>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>; // Guess
			d-tlb-size = <32>; // Guess

			phandle = <0x00000004>;
			/* Hart-Level Interrupt Controller: Every interrupt is
			 * ultimately routed through a hart's HLIC before it
			 * interrupts that hart. */
			HLIC0: interrupt-controller {
				#interrupt-cells = <1>;
				interrupt-controller; /* Receives interrupts */
				compatible = "riscv,cpu-intc";
				phandle = <0x5>;
			};
		};
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
			};
		};
	};
	/* Memory layout:
	 *
	 * [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
	 * [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
	 * [0x0_8000_0000, 0x0_b000_0000) -> RAM memory (768 MiB)
	 * [0x0_b000_0000, 0x0_c000_0000) -> Broken? (256 MiB)
	 * [0x0_c000_0000, 0x1_0000_0000) -> Empty (1024 MiB)
	 * [0x1_0000_0000, 0x1_c000_0000) -> PMEM (3072 MiB)
	 * [0x1_c000_0000, 0x2_8000_0000) -> Empty (3072 MiB)
	 */
	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x30000000>;
	};
	reserved-memory {
		#address-cells = <2>; /* Starting address and size */
		#size-cells = <2>; /* 64 bits memory addresses */
		ranges;
		eth_pool: dma_pool@60000000 {
			reg = <0x0 0x60000000 0x0 0x10000000>;
			compatible = "shared-dma-pool";
		};
		onic_pool: dma_pool@70000000 {
			reg = <0x0 0x70000000 0x0 0x10000000>;
			compatible = "shared-dma-pool";
		};
	};
	dma_clk: dma_clk {
		compatible = "fixed-clock";
		#clock-cells = <0x00000000>;
		clock-frequency = <0x09502f90>;
		phandle = <0x00000002>;
	};
	pmem@100000000 {
		/* volatile; This property indicates that this region is
		 * actually backed by non-persistent memory. This lets the OS
		 * know that it may skip the cache flushes required to ensure
		 * data is made persistent after a write. */
		volatile;
		compatible = "pmem-region";
		reg = <0x1 0x00000000 0x0 0xc0000000>;
	};
	soc {
		#address-cells = <0x00000002>;
		#size-cells = <0x00000002>;
		compatible = "BSC,Lagarto-ox-soc", "simple-bus";
		ranges;

		/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
		 * consoles */

		/* The serial for the kernel console */
		uart_console: serial@UART0_ADDR_HEX {
			compatible = "ns16550";
			reg = <0x0 UART0_ADDR 0x0 0x1000>;
			reg-shift = <2>;
			/* No interrupts for this UART, use console=hvc0 */
			/* This clock is the SERIAL_CLK */
			clock-frequency = <CPU_CLOCK_FREQUENCY>;
			current-speed = <UART_SPEED>;
			status = "okay";
		};
		/* The serial for interrupt tests */
		uart_testing: serial@40003000 {
			compatible = "ns16550";
			reg = <0x0 0x40003000 0x0 0x1000>;
			reg-shift = <2>;
			/* Output interrupt 1 (the first one) */
			interrupts = <1>;
			interrupt-parent = <&PLIC>;
			clock-frequency = <CPU_CLOCK_FREQUENCY>;
			current-speed = <UART_SPEED>;
			status = "okay";
		};

		ethernet0 {
				xlnx,rxmem = <0x000005f2>;
				carv,mtu = <0x000005dc>;
				carv,no-mac;
				device_type = "network";
				// 02:$node:00:01:00:$fpga -> 02:05:00:01:00:02
				// 10.5.1.$N/16 -> 10.5.1.184/16
				// N = 150 + ($node - 1) * 8 + $fpga
				local-mac-address = [00 00 00 00 00 00];
				axistream-connected = <&axi_dma>;
				compatible = "xlnx,xxv-ethernet-1.0-carv";
				memory-region = <&eth_pool>;
		};

		axi_dma: dma@40400000 {
			xlnx,include-dre;
			#dma-cells = <0x00000001>;
			compatible = "xlnx,axi-dma-1.00.a";
			clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
			clocks = <&dma_clk>, <&dma_clk>, <&dma_clk>, <&dma_clk>;
			reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&PLIC>;
			interrupts = <2 3>;
			xlnx,addrwidth = <0x28>;
			xlnx,include-sg;
			xlnx,sg-length-width = <0x17>;
			dma-channel@40400000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0>;
				interrupts = <2>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
				xlnx,include-dre;
			};
			dma-channel@40400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <1>;
				interrupts = <3>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
				xlnx,include-dre;
			};
		};

		/* Platform-Level Interrupt Controller: Delivers interrupts to
		 * HARTs. */
		PLIC: plic@40800000 {
			compatible = "riscv,plic0";
			interrupt-controller; /* Receives interrupts */
			#address-cells = <0>;
			#interrupt-cells = <1>;
			/* Sends interrupts to HART interrupt controllers.
			 * Configures two output targets or contexts:
			 *  - context 0: machine mode external interrupt (11)
			 *  - context 1: supervisor mode external interrupt (9)
			 */
			interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
			reg = < 0x0 0x40800000 0x0 0x00400000>;
			riscv,ndev = <4>;
			//riscv,max-priority = <0x7>;
			phandle = <0x3>;
		};
		/* Core Local Interruptor: It directly connects to the timer and
		 * inter-processor interrupt lines of various HARTs (or CPUs) so
		 * RISC-V per-HART (or per-CPU) local interrupt controller is
		 * the parent interrupt controller for CLINT device. The clock
		 * frequency of CLINT is specified via "timebase-frequency" DT
		 * property of "/cpus" DT node. The "timebase-frequency" DT
		 * property is described in
		 * Documentation/devicetree/bindings/riscv/cpus.yaml
		 */
		clint: clint@40100000 {
			reg = <0x0 0x40100000 0x0 0x00010000>;
			reg-names = "control";
			interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
			compatible = "riscv,clint0";
		};

		/* There is another auxiliar clint (timer) at 40010000 for
		 * tests, but we don't tell the kernel so we can use it for
		 * testing interrupts manually. */
		#if 0
		aux_timer: clint@40010000 {
			reg = <0x0 0x40010000 0x0 0x00010000>;
			reg-names = "control";
			interrupts = <4>; /* PLIC input source 4 */
			interrupt-parent = <&PLIC>;
			compatible = "riscv,clint0";
		};
		#endif

		#ifdef ENABLE_SPI
		uart16750: serial@40005000 {
			compatible = "ns16750";
			reg = <0x00000000 0x40005000 0x00000000 0x00001000>;
			interrupt-parent = <&PLIC>;
			interrupts = <5>;
			clock-frequency = <CPU_CLOCK_FREQUENCY>;
			current-speed = <0x0001c200>;
			status = "okay";
		};
		spi0: spi@40007000 {
			compatible = "ti,keystone-spi";
			reg = <0x00000000 0x40007000 0x00000000 0x00001000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&PLIC>;
			interrupt-names = "intvec0", "intvec1";
			interrupts = <6 0>, <0x00000007 0>;
			ti,davinci-spi-intr-line = <0>;
			spi-max-frequency = <24000000>;
			loopback-mode = <1>;
			status = "okay";
		}; 
		#endif
	};
};