nixos-riscv/ox-plic.dts

/dts-v1/;
/ {
	#address-cells = <0x00000002>;
	#size-cells = <0x00000002>;
	compatible = "riscv,rv64i";
	model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
	chosen {
		bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
	};
	cpus {
		#address-cells = <0x00000001>;
		#size-cells = <0x00000000>;
		timebase-frequency = <0x0000c350>;
		CPU0: cpu@0 {
			clock-frequency = <0x02FAF080>;
			device_type = "cpu";
			reg = <0x00000000>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafd";
			mmu-type = "riscv,sv39";
			tlb-split;
			phandle = <0x00000004>;
			L3: interrupt-controller {
				#interrupt-cells = <0x00000001>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x00000005>;
			};
		};
	};
	/* Memory layout:
	 *
	 * [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
	 * [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
	 * [0x0_8000_0000, 0x0_f7e0_0000) -> RAM memory (~1.8 GiB)
	 * [0x0_f7e0_0000, 0x1_b7f0_0000) -> PMEM3 (3 GiB)
	 * [0x1_b7f0_0000, 0x1_bff0_0000) -> PMEM2 (128 MiB)
	 * [0x1_bff0_0000, 0x2_8000_0000) -> PMEM (3 GiB)
	 */
	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
	};
	reserved-memory {
		#address-cells = <0x00000002>;
		#size-cells = <0x00000002>;
		ranges;
		eth_pool: dma_pool@60000000 {
			reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
			compatible = "shared-dma-pool";
			phandle = <0x00000001>;
		};
		onic_pool: dma_pool@70000000 {
			reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
			compatible = "shared-dma-pool";
			phandle = <0x00000006>;
		};
	};
	eth0_clk: eth0_clk {
		compatible = "fixed-clock";
		#clock-cells = <0x00000000>;
		clock-frequency = <0x09502f90>;
		phandle = <0x00000002>;
	};
	pmem@1bff00000 {
		volatile;
		compatible = "pmem-region";
		reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
	};
	pmem2@1b7f00000 {
		#address-cells = <0x00000002>;
		#size-cells = <0x00000002>;
		volatile;
		compatible = "pmem-region";
		reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
	};
	pmem3@f7e00000 {
		volatile;
		compatible = "pmem-region";
		reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
	};
	soc {
		#address-cells = <0x00000002>;
		#size-cells = <0x00000002>;
		compatible = "BSC,Lagarto-ox-soc", "simple-bus";
		ranges;
		SERIAL: serial@40001000 {
			compatible = "ns16550";
			reg = <0x0 0x40001000 0x0 0x00000100>;
			interrupts = <0>;
			/*port-number = <0>;*/
			reg-shift = <2>;
			clock-frequency = <50000000>;
			current-speed = <115200>;
			status = "okay";
			phandle = <0x00000007>;
		};
		ethernet0 {
			xlnx,rxmem = <0x000005f2>;
			carv,mtu = <0x000005dc>;
			carv,no-mac;
			device_type = "network";
			local-mac-address = [02 05 00 01 00 05];
			axistream-connected = <0x000000fe>;
			compatible = "xlnx,xxv-ethernet-1.0-carv";
			memory-region = <&eth_pool>;
		};
		dma@40400000 {
			xlnx,include-dre;
			phandle = <0x000000fe>;
			#dma-cells = <0x00000001>;
			compatible = "xlnx,axi-dma-1.00.a";
			clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
			clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
			reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&PLIC0>;
			interrupts = <0x00000002 0x00000003>;
			xlnx,addrwidth = <0x00000028>;
			xlnx,include-sg;
			xlnx,sg-length-width = <0x00000017>;
			dma-channel@40400000 {
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0x00000000>;
				interrupts = <0x00000002>;
				xlnx,datawidth = <0x00000040>;
				xlnx,device-id = <0x00000000>;
				xlnx,include-dre;
			};
			dma-channel@40400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x00000001>;
				interrupts = <0x00000003>;
				xlnx,datawidth = <0x00000040>;
				xlnx,device-id = <0x00000000>;
				xlnx,include-dre;
			};
		};
		clint@40002000 {
			reg-names = "control";
			interrupts-extended =
				<&CPU0      0x3>,      <&CPU0 0x7>,
				<&L3        0x3>,        <&L3 0x7>,
				<&onic_pool 0x3>, <&onic_pool 0x7>,
				<&SERIAL    0x3>,    <&SERIAL 0x7>;
			compatible = "riscv,clint0";
			#interrupt-cells = <0x00000001>;
			reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
		};
		PLIC0: plic@40800000 {
			#interrupt-cells = <1>;
			compatible = "riscv,plic0";
			interrupt-controller;
			interrupts-extended = <&L3 3 &L3 7>;
			reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
			riscv,ndev = <0x00000003>;
			riscv,max-priority = <0x00000007>;
			phandle = <0x00000003>;
		};
	};
};