nixos-riscv/dts/lagarto_ox.dts

#include "lagarto_ox.h"

/dts-v1/;
/ {
	#address-cells = <2>;
	#size-cells = <2>; /* 64 bits memory addresses */
	compatible = "riscv,rv64i";
	model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		timebase-frequency = <RTC_FREQ>;
		CPU0: cpu@0 {
			clock-frequency = <CPU_FREQ>;
			device_type = "cpu";
			reg = <0>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafd";
			mmu-type = "riscv,sv39";
			tlb-split;

			i-cache-block-size = <64>; // Guess
			i-cache-sets = <4>;
			i-cache-size = <16384>;
			i-tlb-sets = <1>; // Guess
			i-tlb-size = <32>; // Guess

			d-cache-block-size = <64>; // Guess
			d-cache-sets = <4>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>; // Guess
			d-tlb-size = <32>; // Guess

			/* Hart-Level Interrupt Controller: Every interrupt is
			 * ultimately routed through a hart's HLIC before it
			 * interrupts that hart. */
			HLIC0: interrupt-controller {
				#interrupt-cells = <1>;
				interrupt-controller; /* Receives interrupts */
				compatible = "riscv,cpu-intc";
			};
		};
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
			};
		};
	};
	memory@MEM_ADDR {
		device_type = "memory";
		reg = /bits/ 64 <MEM_ADDR MEM_SIZE>;
	};
	reserved-memory {
		#address-cells = <2>; /* Starting address and size */
		#size-cells = <2>; /* 64 bits memory addresses */
		ranges;
		eth_pool: dma_pool@ETHPOOL_ADDR {
			reg = /bits/ 64 <ETHPOOL_ADDR ETHPOOL_SIZE>;
			compatible = "shared-dma-pool";
		};
		onic_pool: dma_pool@ONICPOOL_ADDR {
			reg = /bits/ 64 <ONICPOOL_ADDR ONICPOOL_SIZE>;
			compatible = "shared-dma-pool";
		};
	};
	pmem@PMEM_ADDR {
		/* volatile; This property indicates that this region is
		 * actually backed by non-persistent memory. This lets the OS
		 * know that it may skip the cache flushes required to ensure
		 * data is made persistent after a write. */
		volatile;
		compatible = "pmem-region";
		reg = /bits/ 64 <PMEM_ADDR PMEM_SIZE>;
	};
	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "BSC,Lagarto-ox-soc", "simple-bus";
		ranges;

		/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
		 * consoles */

#ifdef ENABLE_UART0
		/* The serial for the kernel console */
		uart_console: serial@UART0_ADDR {
			compatible = "ns16550";
			reg = /bits/ 64 <UART0_ADDR UART0_SIZE>;
			reg-shift = <2>;
			/* No interrupts for this UART, use console=hvc0 */
			/* This clock is the SERIAL_CLK */
			clock-frequency = <CPU_FREQ>;
			current-speed = <UART0_SPEED>;
			status = "okay";
		};
#endif /* ENABLE_UART0 */

#ifdef ENABLE_UART1
		/* The serial for interrupt tests */
		uart_testing: serial@UART1_ADDR {
			compatible = "ns16550";
			reg = /bits/ 64 <UART1_ADDR UART1_SIZE>;
			reg-shift = <2>;
			/* Output interrupt 1 (the first one) */
			interrupts = <1>;
			interrupt-parent = <&PLIC>;
			clock-frequency = <CPU_FREQ>;
			current-speed = <UART1_SPEED>;
			status = "okay";
		};
#endif /* ENABLE_UART1 */

#ifdef ENABLE_ETHERNET
		ethernet0 {
			xlnx,rxmem = <1522>;
			carv,mtu = <1500>;
			carv,no-mac;
			device_type = "network";
			// 02:$node:00:01:00:$fpga -> 02:05:00:01:00:02
			// 10.5.1.$N/16 -> 10.5.1.184/16
			// N = 150 + ($node - 1) * 8 + $fpga
			local-mac-address = [00 00 00 00 00 00];
			axistream-connected = <&axi_dma>;
			compatible = "xlnx,xxv-ethernet-1.0-carv";
			memory-region = <&eth_pool>;
		};
#endif /* ENABLE_ETHERNET */

#ifdef ENABLE_AXIDMA
		dma_clk: dma_clk {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <AXIDMA_FREQ>;
		};
		axi_dma: dma@AXIDMA_ADDR {
			reg = /bits/ 64 <AXIDMA_ADDR AXIDMA_SIZE>;
			reg-shift = <2>;
			#address-cells = <2>;
			#size-cells = <2>;
			xlnx,include-dre;
			#dma-cells = <0x1>;
			compatible = "xlnx,axi-dma-1.00.a";
			clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
				"m_axi_s2mm_aclk", "m_axi_sg_aclk";
			clocks = <&dma_clk>, <&dma_clk>, <&dma_clk>, <&dma_clk>;
			interrupt-names = "mm2s_introut", "s2mm_introut";
			interrupt-parent = <&PLIC>;
			interrupts = <2 3>;
			xlnx,addrwidth = <0x28>;
			xlnx,include-sg;
			xlnx,sg-length-width = <0x17>;
			dma-channel@AXIDMA_CH0 {
				reg = /bits/ 64 <AXIDMA_CH0 0x30>;
				compatible = "xlnx,axi-dma-mm2s-channel";
				dma-channels = <0>;
				interrupts = <2>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
				xlnx,include-dre;
			};
			dma-channel@AXIDMA_CH1 {
				reg = /bits/ 64 <AXIDMA_CH1 0x30>;
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <1>;
				interrupts = <3>;
				xlnx,datawidth = <0x40>;
				xlnx,device-id = <0x0>;
				xlnx,include-dre;
			};
		};
#endif /* ENABLE_AXIDMA */

#ifdef ENABLE_PLIC
		/* Platform-Level Interrupt Controller: Delivers interrupts to
		 * HARTs. */
		PLIC: plic@PLIC_ADDR {
			reg = /bits/ 64 <PLIC_ADDR PLIC_SIZE>;
			compatible = "riscv,plic0";
			interrupt-controller; /* Receives interrupts */
			#address-cells = <0>;
			#interrupt-cells = <1>;
			/* Sends interrupts to HART interrupt controllers.
			 * Configures two output targets or contexts:
			 *  - context 0: machine mode external interrupt (11)
			 *  - context 1: supervisor mode external interrupt (9)
			 */
			interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
			riscv,ndev = <PLIC_NDEV>;
			//riscv,max-priority = <0x7>;
		};
#endif /* ENABLE_PLIC */

#ifdef ENABLE_CLINT
		/* Core Local Interruptor: It directly connects to the timer and
		 * inter-processor interrupt lines of various HARTs (or CPUs) so
		 * RISC-V per-HART (or per-CPU) local interrupt controller is
		 * the parent interrupt controller for CLINT device. The clock
		 * frequency of CLINT is specified via "timebase-frequency" DT
		 * property of "/cpus" DT node. The "timebase-frequency" DT
		 * property is described in
		 * Documentation/devicetree/bindings/riscv/cpus.yaml
		 */
		clint: clint@CLINT_ADDR {
			reg = /bits/ 64 <CLINT_ADDR CLINT_SIZE>;
			reg-names = "control";
			interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
			compatible = "riscv,clint0";
		};
#endif /* ENABLE_CLINT */

#if 0
		/* There is another auxiliar clint (timer) at 40010000 for
		 * tests, but we don't tell the kernel so we can use it for
		 * testing interrupts manually. */
		aux_timer: clint@AUXTIMER_ADDR {
			reg = /bits/ 64 <AUXTIMER_ADDR AUXTIMER_SIZE>;
			reg-names = "control";
			interrupts = <4>; /* PLIC input source 4 */
			interrupt-parent = <&PLIC>;
			compatible = "riscv,clint0";
		};
#endif

#ifdef ENABLE_SPI
		serial@UART2_ADDR {
			compatible = "ns16750";
			reg = /bits/ 64 <UART2_ADDR UART2_SIZE>;
			interrupt-parent = <&PLIC>;
			interrupts = <5>;
			clock-frequency = <CPU_FREQ>;
			current-speed = <UART2_SPEED>;
			status = "okay";
		};
		spi@SPI_ADDR {
			compatible = "ti,keystone-spi";
			reg = /bits/ 64 <SPI_ADDR SPI_SIZE>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&PLIC>;
			interrupt-names = "intvec0", "intvec1";
			interrupts = <6 0>, <7 0>;
			ti,davinci-spi-intr-line = <0>;
			spi-max-frequency = <24000000>;
			loopback-mode = <1>;
			status = "okay";
		}; 
#endif /* ENABLE_SPI */

	};
};