nixos-riscv/ox-plic.dts

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/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>; /* 64 bits memory addresses */
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compatible = "riscv,rv64i";
model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
aliases {
serial0 = &uart_console; // ttyS0
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// serial1 = &uart_testing; // ttyS1
};
// chosen {
// bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
// };
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cpus {
#address-cells = <1>;
#size-cells = <0>;
/* Timer */
timebase-frequency = <50000>; /* 50 kHz */
CPU0: cpu@0 {
clock-frequency = <50000000>; /* 50 MHz */
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafd";
mmu-type = "riscv,sv39";
tlb-split;
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// OpenPiton+Ariane Platform
// L1I Size / Assoc: 16 kB / 4
// L1D Size / Assoc: 32 kB / 4
// L15 Size / Assoc: 128 kB / 8
// L2 Size / Assoc: 256 kB / 4
// L15/L1D Cacheline size 64
i-cache-block-size = <64>; // Guess
i-cache-sets = <4>;
i-cache-size = <16384>;
i-tlb-sets = <1>; // Guess
i-tlb-size = <32>; // Guess
d-cache-block-size = <64>; // Guess
d-cache-sets = <4>;
d-cache-size = <32768>;
d-tlb-sets = <1>; // Guess
d-tlb-size = <32>; // Guess
phandle = <0x00000004>;
/* Hart-Level Interrupt Controller: Every interrupt is
* ultimately routed through a hart's HLIC before it
* interrupts that hart. */
HLIC0: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller; /* Receives interrupts */
compatible = "riscv,cpu-intc";
phandle = <0x5>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
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};
};
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};
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/* Memory layout:
*
* [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
* [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
* [0x0_8000_0000, 0x0_fff0_0000) -> RAM memory (2047 MiB)
* [0x0_fff0_0000, 0x1_0000_0000) -> Empty (1 MiB)
* [0x1_0000_0000, 0x1_c000_0000) -> PMEM (3072 MiB)
* [0x1_c000_0000, 0x2_8000_0000) -> Empty (3072 MiB)
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*/
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memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x7ff00000>;
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};
reserved-memory {
#address-cells = <2>; /* Starting address and size */
#size-cells = <2>; /* 64 bits memory addresses */
ranges;
eth_pool: dma_pool@60000000 {
reg = <0x0 0x60000000 0x0 0x10000000>;
compatible = "shared-dma-pool";
};
onic_pool: dma_pool@70000000 {
reg = <0x0 0x70000000 0x0 0x10000000>;
compatible = "shared-dma-pool";
};
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};
// eth0_clk: eth0_clk {
// compatible = "fixed-clock";
// #clock-cells = <0x00000000>;
// clock-frequency = <0x09502f90>;
// phandle = <0x00000002>;
// };
pmem@100000000 {
Remove unused PMEM regions Boots until the init, then fails with: [ 42.561840] Freeing unused kernel image (initmem) memory: 2448K [ 42.572360] Run /init as init process [ 42.577400] with arguments: [ 42.581780] /init [ 42.584520] with environment: [ 42.589320] HOME=/ [ 42.592140] TERM=linux [ 42.637580] init[1]: unhandled signal 4 code 0x1 at 0x0000003f966980d8 in ld-linux-riscv64-lp64d.so.1[3f96683000+23000] [ 42.650580] CPU: 0 PID: 1 Comm: init Not tainted 6.1.62 #1-NixOS [ 42.657720] Hardware name: Barcelona Supercomputing Center - Lagarto Ox (NixOS) (DT) [ 42.666760] epc : 0000003f966980d8 ra : 0000000000000000 sp : 0000003fe5c95db0 [ 42.675040] gp : ffffffff8197ea48 tp : 0000000000000000 t0 : 0000000000000000 [ 42.683320] t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000000000000000 [ 42.691600] s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000 [ 42.699880] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 [ 42.708160] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 [ 42.716420] s2 : 0000000000000000 s3 : 0000000000000000 s4 : 0000000000000000 [ 42.724700] s5 : 0000000000000000 s6 : 0000000000000000 s7 : 0000000000000000 [ 42.733380] s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000 [ 42.741660] s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 [ 42.749920] t5 : 0000000000000000 t6 : 0000000000000000 [ 42.756440] status: 0000000200004020 badaddr: 0000000000010513 cause: 0000000000000002 [ 42.767620] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 [ 42.775720] CPU: 0 PID: 1 Comm: init Not tainted 6.1.62 #1-NixOS [ 42.782320] Hardware name: Barcelona Supercomputing Center - Lagarto Ox (NixOS) (DT) [ 42.790460] Call Trace: [ 42.793380] [<ffffffff800070c4>] dump_backtrace+0x38/0x48 [ 42.799520] [<ffffffff809f063c>] show_stack+0x50/0x68 [ 42.805280] [<ffffffff809fd1f8>] dump_stack_lvl+0x60/0x84 [ 42.811400] [<ffffffff809fd23c>] dump_stack+0x20/0x30 [ 42.817140] [<ffffffff809f0918>] panic+0x160/0x390 [ 42.822620] [<ffffffff80020184>] do_exit+0xa70/0xa78 [ 42.828260] [<ffffffff800203a4>] do_group_exit+0x44/0xb0 [ 42.834240] [<ffffffff80031eec>] get_signal+0x9b4/0xa00 [ 42.840140] [<ffffffff80005ca0>] do_work_pending+0x18c/0x610 [ 42.846480] [<ffffffff80003880>] resume_userspace_slow+0x10/0x14 [ 42.853420] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 ]---
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/* volatile; This property indicates that this region is
* actually backed by non-persistent memory. This lets the OS
* know that it may skip the cache flushes required to ensure
* data is made persistent after a write. */
volatile;
compatible = "pmem-region";
reg = <0x1 0x00000000 0x0 0xc0000000>;
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};
soc {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "BSC,Lagarto-ox-soc", "simple-bus";
ranges;
/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
* consoles */
/* The serial for the kernel console */
uart_console: serial@40001000 {
compatible = "ns16550";
reg = <0x0 0x40001000 0x0 0x1000>;
interrupts = <1>; /* Output interrupt 1 */
interrupt-parent = <&PLIC>;
reg-shift = <2>;
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/* No interrupts for this UART, use console=hvc0 */
/* This clock is the SERIAL_CLK */
clock-frequency = <50000000>;
current-speed = <115200>;
status = "okay";
};
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// /* The serial for interrupt tests */
// uart_testing: serial@40003000 {
// compatible = "ns16550";
// reg = <0x0 0x40003000 0x0 0x1000>;
// interrupts = <1>; /* Output interrupt 1 */
// interrupt-parent = <&PLIC>;
// reg-shift = <2>;
// clock-frequency = <50000000>;
// current-speed = <115200>;
// status = "okay";
// };
// ethernet0 {
// xlnx,rxmem = <0x000005f2>;
// carv,mtu = <0x000005dc>;
// carv,no-mac;
// device_type = "network";
// local-mac-address = [02 05 00 01 00 05];
// axistream-connected = <0x000000fe>;
// compatible = "xlnx,xxv-ethernet-1.0-carv";
// memory-region = <&eth_pool>;
// };
// dma@40400000 {
// xlnx,include-dre;
// phandle = <0x000000fe>;
// #dma-cells = <0x00000001>;
// compatible = "xlnx,axi-dma-1.00.a";
// clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
// clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
// reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
// interrupt-names = "mm2s_introut", "s2mm_introut";
// interrupt-parent = <&PLIC>;
// interrupts = <2 3>;
// xlnx,addrwidth = <0x00000028>;
// xlnx,include-sg;
// xlnx,sg-length-width = <0x00000017>;
// dma-channel@40400000 {
// compatible = "xlnx,axi-dma-mm2s-channel";
// dma-channels = <0x00000000>;
// interrupts = <0x00000002>;
// xlnx,datawidth = <0x00000040>;
// xlnx,device-id = <0x00000000>;
// xlnx,include-dre;
// };
// dma-channel@40400030 {
// compatible = "xlnx,axi-dma-s2mm-channel";
// dma-channels = <0x00000001>;
// interrupts = <0x00000003>;
// xlnx,datawidth = <0x00000040>;
// xlnx,device-id = <0x00000000>;
// xlnx,include-dre;
// };
// };
/* Platform-Level Interrupt Controller: Delivers interrupts to
* HARTs. */
PLIC: plic@40800000 {
compatible = "riscv,plic0";
interrupt-controller; /* Receives interrupts */
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#address-cells = <0>;
#interrupt-cells = <1>;
/* Sends interrupts to HART interrupt controllers */
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/*
* From: linux-6.6.1/arch/riscv/include/asm/csr.h
*
* Interrupt causes (minus the high bit)
* #define IRQ_S_SOFT 1
* #define IRQ_VS_SOFT 2
* #define IRQ_M_SOFT 3
* #define IRQ_S_TIMER 5
* #define IRQ_VS_TIMER 6
* #define IRQ_M_TIMER 7
* #define IRQ_S_EXT 9
* #define IRQ_VS_EXT 10
* #define IRQ_M_EXT 11
* #define IRQ_S_GEXT 12
* #define IRQ_PMU_OVF 13
* #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
* #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
*/
interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
reg = < 0x0 0x40800000 0x0 0x00400000>;
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riscv,ndev = <3>;
//riscv,max-priority = <0x7>;
phandle = <0x3>;
};
/* Core Local Interruptor: It directly connects to the timer and
* inter-processor interrupt lines of various HARTs (or CPUs) so
* RISC-V per-HART (or per-CPU) local interrupt controller is
* the parent interrupt controller for CLINT device. The clock
* frequency of CLINT is specified via "timebase-frequency" DT
* property of "/cpus" DT node. The "timebase-frequency" DT
* property is described in
* Documentation/devicetree/bindings/riscv/cpus.yaml
*/
timer@40002000 {
reg = <0x0 0x40002000 0x0 0x000c0000>;
reg-names = "control";
interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
/*<&CPU0 0x3>, <&CPU0 0x7>,*/
/*<&onic_pool 0x3>, <&onic_pool 0x7>,*/
/*<&SERIAL 0x3>, <&SERIAL 0x7>*/
compatible = "riscv,clint0";
};
/* Guesswork: There must be a timer at 0x40170000 as it is
* initialized in OpenSBI. It seems to drive the console. */
//SERIAL_CLK: timer@40170000 {
// clock-frequency = <100000000>;
// clocks = <&clk_bus_0>;
// compatible = "xlnx,xps-timer-1.00.a";
// interrupt-parent = <&axi_intc_1>;
// interrupts = <2 2>;
// reg = <0x41c00000 0x10000>;
// xlnx,count-width = <0x20>;
// xlnx,one-timer-only = <0x0>;
//};
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};
};