Commit Graph

43 Commits

Author SHA1 Message Date
3bcc4255db Add SPEC launcher 2024-10-09 15:52:46 +02:00
ce70726bf6 Build specinvoke from source
The one contained in the CPU SPEC ISO is built for x86, and there is no
binary for RISC-V.
2024-10-08 10:13:27 +02:00
d7ef22936a Add SPEC CPU mini with a subset of benchmarks 2024-10-07 13:33:53 +02:00
a9350da4b8 Add SPEC CPU 2017 benchmarks 2024-10-07 09:23:28 +02:00
af666c44ef Add plic claim baremetal test 2024-10-02 07:33:57 +02:00
8780098a29 Add stream benchmark 2024-09-25 13:08:40 +02:00
f8eb8b8d52 Add rvb package 2024-09-25 10:20:55 +02:00
8047a6a4eb Add llvm-epi clang compiler 2024-09-25 10:18:14 +02:00
2fab6b8ec0 Update bitstream to ox_u55c_87a14c32
This bitstream attempts to fix the PLIC issues with the threshold
register, so we should see the PLIC tests success now.

See: https://gitlab.bsc.es/hwdesign/fpga/integration-lab/fpga-shell/-/issues/147
2024-09-19 11:01:48 +02:00
3dad4fb3d1 Move patches to its own directory 2024-09-06 08:22:14 +02:00
e2c770208e Move other tools to tools/ 2024-09-06 08:11:24 +02:00
3ee0933d7b Add plictool to dump PLIC state 2024-09-03 15:59:04 +02:00
58ddfd4720 Dump registers in baremetal plic supervisor test 2024-08-29 16:06:07 +02:00
ebcef525ba Update bitstream to try to fix delegation (again) 2024-08-29 13:44:11 +02:00
65b91368d6 Update baremetal tests to sv_eirq branch 2024-08-28 10:19:58 +02:00
8b491f519b Add trampoline scripts to CI 2024-08-26 17:58:03 +02:00
8272212769 Add custom bootrom 2024-08-23 16:06:21 +02:00
44de310116 Switch to ox_u55c_f6b4a076 bitstream 2024-08-23 16:06:21 +02:00
Rodrigo Arias Mallo
7b75cd2563 Add UART patch for FPGA in sa-fpga tests 2024-08-23 13:23:33 +02:00
Rodrigo Arias Mallo
9177f610a7 Add FPGA baremetal tests 2024-08-22 17:12:42 +02:00
f617efdcac Add memtool program to test the memory 2024-07-09 15:16:05 +02:00
5b34b3b97b Add csrtool to view and change CSR registers 2024-07-08 19:19:05 +02:00
5f90528b51 Add bootrom support 2024-07-08 18:11:11 +02:00
1f0ac64631 Add bitstream to Nix 2024-07-08 13:46:37 +02:00
f554a154b7 WIP 2024-05-28 18:12:14 +02:00
4d284ae315 Move qemu specific config to vm.nix 2024-03-07 12:03:02 +01:00
3b68bfda47 Add Lagarto Hun configuration 2024-03-01 18:33:30 +01:00
5bb469d1a4 Add FPGA OpenSBI and U-Boot 2024-03-01 18:19:59 +01:00
960badad9b Enable recommended options in the kernel 2024-01-25 15:37:50 +01:00
9db6d05222 Remove old stdenv hack for the kernel 2024-01-25 15:37:18 +01:00
b7251e7a84 Build OpenSBI and u-boot without vector extension 2024-01-25 15:36:39 +01:00
c0ecd32173 Remove unneeded override of stdenv
The march and mtune flags are passed by the crossSystem gcc attributes,
which are placed *before* the flags to gcc. This may end up causing some
packages to break, but it is working fine so far.
2024-01-24 10:00:19 +01:00
3707e5708e Disable EFI in the kernel and use normal stdenv
In order to build the kernel without compressed instructions we need to
disable EFI support. We also need to leave the kernel to figure the
proper -march and -mabi flags, as otherwise it fails to build. Using the
option "CONFIG_RISCV_ISA_C n" disables the use of compressed
instructions.
2024-01-22 13:37:00 +01:00
a333210fdc Only change cross stdenv
Prevents mass rebuilds in x86, where the envvar doesn't have any effect.
2024-01-19 17:10:22 +01:00
635935cd09 Build packages without compressed instructions 2024-01-19 16:35:45 +01:00
98d04ee398 Also build u-boot ELF file for debugging 2024-01-19 16:32:40 +01:00
819c7e6e93 Build u-boot and the kernel without compressed 2024-01-19 16:31:53 +01:00
1fda5d7710 Set the bootcmd in u-boot
In QEMU the kernel is loaded at the ${kernel_addr_r} address and we need
to use booti instead of bootm.
2024-01-19 14:29:23 +01:00
9a475bc1e3 Booting Linux and userspace OK 2024-01-19 12:35:05 +01:00
2f387d3362 Use custom u-boot build 2024-01-18 17:58:00 +01:00
5dbb297adf Fix qemu without rutabagaSupport 2024-01-18 15:59:51 +01:00
6f6e735ba7 Fix cross build of systemd 254.6 2024-01-18 14:13:42 +01:00
Rodrigo Arias Mallo
f8b624af67 Boot opensbi without compressed 2024-01-17 18:22:30 +01:00