Update baremetal tests to sv_eirq branch
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@ -79,8 +79,8 @@ final: prev:
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name = "sa-fpga-tests";
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src = builtins.fetchGit {
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url = "git@gitlab-internal.bsc.es:hwdesign/rtl/core-tile/sa-fpga.git";
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rev = "6547e63f3aed312a4c36f093b5e6421c7f1704f6";
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ref = "ni/supervisor_tests";
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rev = "afe0372413a94fff279ca5d5002c3e999ac8defb";
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ref = "ft/sv_eirq";
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};
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dontConfigure = true;
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patches = [
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