Commit Graph

245 Commits

Author SHA1 Message Date
Rodrigo Arias Mallo
64cc2a982f Clear MIP before enabling timer 2024-08-21 10:09:06 +02:00
Rodrigo Arias Mallo
90df8a3ccb Add stvec trap 2024-08-21 10:03:19 +02:00
Rodrigo Arias Mallo
baf45e6749 Dump more registers in PLIC test 2024-08-21 09:53:39 +02:00
Rodrigo Arias Mallo
fd2b766760 Improve progress print 2024-08-21 09:39:00 +02:00
Rodrigo Arias Mallo
1faef5b452 Don't enable machine interrupt 2024-08-21 09:29:22 +02:00
Rodrigo Arias Mallo
b7287bd4df Port supervisor PLIC test to OpenSBI 2024-08-21 09:25:07 +02:00
Rodrigo Arias Mallo
298595ba3c Enable also MEIE and MIE 2024-08-21 08:16:14 +02:00
Rodrigo Arias Mallo
a858b3548e Enable SIE in MSTATUS too 2024-08-21 08:08:13 +02:00
Rodrigo Arias Mallo
60631ec37f Enable SEIE in MIE directly from machine mode 2024-08-21 08:00:31 +02:00
Rodrigo Arias Mallo
05eed3af94 Disable MEIE bit in MIE register 2024-08-21 07:56:17 +02:00
Rodrigo Arias Mallo
1419473a08 Dump machine registers in OpenSBI 2024-08-21 07:14:23 +02:00
Rodrigo Arias Mallo
62bd702929 Restore stvec to its original value 2024-08-21 06:24:42 +02:00
Rodrigo Arias Mallo
19dbb857c8 Enable MEIP in OpenSBI 2024-08-03 14:55:35 +02:00
Rodrigo Arias Mallo
91d3e9b163 Set stvec to zero 2024-08-02 16:13:46 +02:00
Rodrigo Arias Mallo
98f794e52d Enable timer command in U-Boot 2024-08-02 15:27:20 +02:00
Rodrigo Arias Mallo
33fb07481a Add exception enable U-Boot command 2024-08-02 13:49:12 +02:00
Rodrigo Arias Mallo
055f03980c Add exception sregs command to U-Boot 2024-08-02 13:18:18 +02:00
Rodrigo Arias Mallo
995b1e3848 Delegate external interrupts to U-Boot 2024-08-02 12:15:47 +02:00
Rodrigo Arias Mallo
e67965cc0a Always enable external machine mode interrupts 2024-08-02 10:33:31 +02:00
Rodrigo Arias Mallo
038d2e7156 Try opensbi without supervisor ext delegation 2024-08-01 20:22:57 +02:00
cd7eb7179f Update journal with PLIC experiments 2024-08-01 19:29:49 +02:00
eee26f2b4d More experiments with OpenSBI 1.5 with debug 2024-07-15 11:02:27 +02:00
9fac87a00e Move FDT to 0xc0000000 2024-07-12 18:59:48 +02:00
8725d04533 Switch OpenSBI to generic 2024-07-12 18:53:16 +02:00
c38edfe737 Enable PLIC 2024-07-12 18:51:17 +02:00
fc7bfddd64 Switch to openpiton configuration 2024-07-12 18:47:48 +02:00
80c93613d2 Try FDT address 0x80013000 2024-07-12 18:40:39 +02:00
d3779d0f95 Revert serial address and move FDT 2024-07-12 18:28:43 +02:00
444bb635f6 Move serial to 0x4000_0000 2024-07-12 18:25:14 +02:00
bed3c7ba5c Disable PLIC from DT 2024-07-12 18:19:58 +02:00
9a7b230b5b Rollback to OpenSBI 1.4 2024-07-12 18:07:25 +02:00
384069130b Reduce OpenSBI trap debug message 2024-07-12 17:50:22 +02:00
7d9f375e4a Remove newline in OpenSBI trap debug line 2024-07-12 17:38:53 +02:00
c6e2db8c2d Add extra debug messages 2024-07-12 16:36:18 +02:00
71c81f8dcd Add debug in OpenSBI trap handler 2024-07-12 16:09:51 +02:00
8819c091eb Remove clint from device tree for now 2024-07-12 14:57:43 +02:00
97c0dd6859 Remove reserved region hack 2024-07-12 14:50:59 +02:00
983dc939ab Move the FDT to 0x80100000 2024-07-12 14:43:09 +02:00
8b2821f2f2 Try setting the mtimecmp address 2024-07-12 14:14:25 +02:00
6a57dd004f Switch to "riscv,aclint-mtimer" timer 2024-07-12 13:55:08 +02:00
6576a92ba5 Debug timer_mtimer_cold_init() in OpenSBI 2024-07-12 13:48:52 +02:00
722f185525 Add timer debug patch for OpenSBI 2024-07-12 13:25:03 +02:00
83df8edd28 Switch to fpga/openpiton in OpenSBI 2024-07-12 12:44:21 +02:00
6604911264 Remove reg-names property from clint 2024-07-12 12:38:34 +02:00
dc8a8c2ce9 Build OpenSBI with the generic platform 2024-07-12 12:20:03 +02:00
8c2b28cf21 Enable systemd debug log and all-in-order 2024-07-12 10:50:28 +02:00
40def167f1 Update journal 2024-07-12 10:20:32 +02:00
c23d33a51c Update to OpenSBI 1.5 2024-07-12 09:34:45 +02:00
9f6f8bcddc Don't use DTB in U-Boot, read it from OpenSBI 2024-07-11 16:05:05 +02:00
5ddea498ca Add reserved segment from 0x80000000 2024-07-11 15:47:29 +02:00