Delegate external interrupts to U-Boot

This commit is contained in:
Rodrigo Arias Mallo 2024-08-02 12:00:24 +02:00
parent e67965cc0a
commit 995b1e3848
3 changed files with 77 additions and 2 deletions

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@ -3297,3 +3297,44 @@ I see that the MIE sets the machine mode external interrupt enable in this way:
Only if the external interrupt function is not the default one. But for the
PLIC, it looks like the default one is being used. So let's enable the machine
mode interrupts unconditionally.
Let's try to cause an interruption. I would need to list all the steps.
mw 0x40802000 0x10 # Enable interrupt for source 4 (timer)
mw 0x40800010 0xff # Make source 4 priority large
md 0x40a00004 1 # Show which value should be claimed
mw 0x40a00004 0 # Claim 0
Nice, I can see the trap:
Boot HART MIDELEG : 0x0000000000000022
Boot HART MEDELEG : 0x000000000000b109
...
=> mw 0x40802000 0x10 # Enable interrupt for source 4 (timer)
=> mw 0x40800010 0xff # Make source 4 priority large
=> md 0x40a00004 1 # Show which value should be claimed
40a00004: 00000000 ....
=> mw 0x40a00004 0 # Claim 0 (weird)
<i
sbi_trap_error: hart0: trap0: unhandled local interrupt (error -1000)
sbi_trap_error: hart0: trap0: mcause=0x800000000000000b mtval=0x0000000000000000
sbi_trap_error: hart0: trap0: mepc=0x00000000af71ebbc mstatus=0x8000000a00006800
sbi_trap_error: hart0: trap0: ra=0x00000000af71eba0 sp=0x00000000aeed3b00
sbi_trap_error: hart0: trap0: gp=0x00000000aeed3dd0 tp=0x0000000000000000
sbi_trap_error: hart0: trap0: s0=0x00000000af7cd170 s1=0x0000000000000000
sbi_trap_error: hart0: trap0: a0=0x0000000000000000 a1=0x0000000000000002
sbi_trap_error: hart0: trap0: a2=0x0000000000000008 a3=0x0000000000000004
sbi_trap_error: hart0: trap0: a4=0x0000000000000001 a5=0x0000000000000001
sbi_trap_error: hart0: trap0: a6=0x0000000000000008 a7=0x00000000af795778
sbi_trap_error: hart0: trap0: s2=0x0000000000000000 s3=0x00000000aeed5b90
sbi_trap_error: hart0: trap0: s4=0x0000000000000003 s5=0x00000000af7f7a4c
sbi_trap_error: hart0: trap0: s6=0x0000000000000000 s7=0x0000000000000000
sbi_trap_error: hart0: trap0: s8=0x0000000000000000 s9=0x0000000000000000
sbi_trap_error: hart0: trap0: s10=0x00000000aeed5bc0 s11=0x0000000000000000
sbi_trap_error: hart0: trap0: t0=0x00000000aeed3ac0 t1=0x0000000000000039
sbi_trap_error: hart0: trap0: t2=0x3b3d74696e695f64 t3=0x0000000000000010
sbi_trap_error: hart0: trap0: t4=0x0000000000000000 t5=0x61745f746f6f627b
sbi_trap_error: hart0: trap0: t6=0x00000000aeed3aa0
Now let's try delegating it to u-boot, and see if I can print some information.

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@ -216,7 +216,10 @@
# url = "file:///home/Computational/rarias/riscv/u-boot";
# rev = "f80a22a480f0e4157647bacf90e663be457c72c4";
#};
#patches = [ ./u-boot-debug.patch ];
patches = [
#./u-boot-debug.patch
./uboot-debug-ext-interrupts.patch
];
#
# CONFIG_SERIAL_PRESENT=n
# CONFIG_SYS_NS16550=n
@ -326,7 +329,7 @@
];
patches = [
./opensbi-timer-debug.patch
./opensbi-dont-delegate.patch
#./opensbi-dont-delegate.patch
#./ox-alveo-platform-plic.patch
];
});

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@ -0,0 +1,31 @@
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6cecadfac5..f649844b23 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -81,7 +81,7 @@ _start:
#if CONFIG_IS_ENABLED(RISCV_MMODE)
li t0, MIE_MSIE
#else
- li t0, SIE_SSIE
+ li t0, (SIE_SSIE + SIE_SEIE + SIE_STIE)
#endif
csrs MODE_PREFIX(ie), t0
#endif
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index a26ccc721f..b8d2a71223 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -193,10 +193,13 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
+ printf("u-boot: got ext interrupt %lu\n", irq);
+ show_regs(regs);
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
case IRQ_S_TIMER:
+ printf("u-boot: got timer interrupt %lu\n", irq);
timer_interrupt(0); /* handle timer interrupt */
break;
default: