Delegate external interrupts to U-Boot
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JOURNAL.md
41
JOURNAL.md
@ -3297,3 +3297,44 @@ I see that the MIE sets the machine mode external interrupt enable in this way:
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Only if the external interrupt function is not the default one. But for the
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PLIC, it looks like the default one is being used. So let's enable the machine
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mode interrupts unconditionally.
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Let's try to cause an interruption. I would need to list all the steps.
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mw 0x40802000 0x10 # Enable interrupt for source 4 (timer)
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mw 0x40800010 0xff # Make source 4 priority large
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md 0x40a00004 1 # Show which value should be claimed
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mw 0x40a00004 0 # Claim 0
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Nice, I can see the trap:
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Boot HART MIDELEG : 0x0000000000000022
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Boot HART MEDELEG : 0x000000000000b109
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...
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=> mw 0x40802000 0x10 # Enable interrupt for source 4 (timer)
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=> mw 0x40800010 0xff # Make source 4 priority large
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=> md 0x40a00004 1 # Show which value should be claimed
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40a00004: 00000000 ....
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=> mw 0x40a00004 0 # Claim 0 (weird)
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<i
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sbi_trap_error: hart0: trap0: unhandled local interrupt (error -1000)
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sbi_trap_error: hart0: trap0: mcause=0x800000000000000b mtval=0x0000000000000000
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sbi_trap_error: hart0: trap0: mepc=0x00000000af71ebbc mstatus=0x8000000a00006800
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sbi_trap_error: hart0: trap0: ra=0x00000000af71eba0 sp=0x00000000aeed3b00
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sbi_trap_error: hart0: trap0: gp=0x00000000aeed3dd0 tp=0x0000000000000000
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sbi_trap_error: hart0: trap0: s0=0x00000000af7cd170 s1=0x0000000000000000
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sbi_trap_error: hart0: trap0: a0=0x0000000000000000 a1=0x0000000000000002
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sbi_trap_error: hart0: trap0: a2=0x0000000000000008 a3=0x0000000000000004
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sbi_trap_error: hart0: trap0: a4=0x0000000000000001 a5=0x0000000000000001
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sbi_trap_error: hart0: trap0: a6=0x0000000000000008 a7=0x00000000af795778
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sbi_trap_error: hart0: trap0: s2=0x0000000000000000 s3=0x00000000aeed5b90
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sbi_trap_error: hart0: trap0: s4=0x0000000000000003 s5=0x00000000af7f7a4c
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sbi_trap_error: hart0: trap0: s6=0x0000000000000000 s7=0x0000000000000000
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sbi_trap_error: hart0: trap0: s8=0x0000000000000000 s9=0x0000000000000000
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sbi_trap_error: hart0: trap0: s10=0x00000000aeed5bc0 s11=0x0000000000000000
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sbi_trap_error: hart0: trap0: t0=0x00000000aeed3ac0 t1=0x0000000000000039
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sbi_trap_error: hart0: trap0: t2=0x3b3d74696e695f64 t3=0x0000000000000010
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sbi_trap_error: hart0: trap0: t4=0x0000000000000000 t5=0x61745f746f6f627b
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sbi_trap_error: hart0: trap0: t6=0x00000000aeed3aa0
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Now let's try delegating it to u-boot, and see if I can print some information.
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@ -216,7 +216,10 @@
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# url = "file:///home/Computational/rarias/riscv/u-boot";
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# rev = "f80a22a480f0e4157647bacf90e663be457c72c4";
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#};
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#patches = [ ./u-boot-debug.patch ];
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patches = [
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#./u-boot-debug.patch
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./uboot-debug-ext-interrupts.patch
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];
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#
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# CONFIG_SERIAL_PRESENT=n
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# CONFIG_SYS_NS16550=n
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@ -326,7 +329,7 @@
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];
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patches = [
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./opensbi-timer-debug.patch
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./opensbi-dont-delegate.patch
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#./opensbi-dont-delegate.patch
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#./ox-alveo-platform-plic.patch
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];
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});
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31
uboot-debug-ext-interrupts.patch
Normal file
31
uboot-debug-ext-interrupts.patch
Normal file
@ -0,0 +1,31 @@
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diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
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index 6cecadfac5..f649844b23 100644
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--- a/arch/riscv/cpu/start.S
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+++ b/arch/riscv/cpu/start.S
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@@ -81,7 +81,7 @@ _start:
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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li t0, MIE_MSIE
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#else
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- li t0, SIE_SSIE
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+ li t0, (SIE_SSIE + SIE_SEIE + SIE_STIE)
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#endif
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csrs MODE_PREFIX(ie), t0
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#endif
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diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
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index a26ccc721f..b8d2a71223 100644
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--- a/arch/riscv/lib/interrupts.c
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+++ b/arch/riscv/lib/interrupts.c
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@@ -193,10 +193,13 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
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switch (irq) {
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case IRQ_M_EXT:
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case IRQ_S_EXT:
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+ printf("u-boot: got ext interrupt %lu\n", irq);
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+ show_regs(regs);
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external_interrupt(0); /* handle external interrupt */
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break;
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case IRQ_M_TIMER:
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case IRQ_S_TIMER:
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+ printf("u-boot: got timer interrupt %lu\n", irq);
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timer_interrupt(0); /* handle timer interrupt */
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break;
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default:
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