nixos-riscv/overlay.nix

final: prev:

# Changes to packages from nixpkgs

{
  clangEpi = final.callPackage ./pkgs/llvm-epi/default.nix { openmp = null; };
  clangEpiUnwrapped = final.callPackage ./pkgs/llvm-epi/clang.nix { };
  stdenvClangEpi = final.stdenv.override { cc = final.buildPackages.clangEpi; allowedRequisites = null; };

  rvb = final.callPackage ./pkgs/rvb/default.nix { };
  rvb-clang = final.callPackage ./pkgs/rvb/default.nix { stdenv = final.stdenvClangEpi; };
  stream = final.callPackage ./pkgs/stream/default.nix { };

  spec-cpu-tools = final.callPackage ./pkgs/spec-cpu/tools.nix { };
  spec-cpu = final.callPackage ./pkgs/spec-cpu/default.nix { };
  spec-cpu-clang = final.callPackage ./pkgs/spec-cpu/default.nix { stdenv = final.stdenvClangEpi; };

  blis = ((prev.blis.override {
    blas64 = true;
    withArchitecture = "generic";
  }).overrideAttrs (old: {
    nativeBuildInputs = (old.nativeBuildInputs or []) ++ [
      prev.buildPackages.gfortran
    ];
  })).overrideDerivation (old : {
    configureFlags = [
      "--enable-cblas"
      "--blas-int-size=64"
      "--enable-threading=openmp"
      #"--build=x86_64-unknown-linux-gnu"
      #"--host=riscv64-unknown-linux-gnu"
      "generic"
    ];
  });

  riscv-tools = prev.pkgsStatic.stdenv.mkDerivation {
    name = "riscv-tools";
    src = ./tools;
    makeFlags = [ "PREFIX=${placeholder "out"}" ];
  };

  bitstreams = builtins.fetchGit {
    url = "git@bscpm03.bsc.es:rarias/bitstreams.git";
    rev = "2f899627a226890c6f9820aa44e34c2ecea03faf";
  };

  # Baremetal tests for standalone FPGA
  sa-fpga-tests = prev.pkgsStatic.stdenv.mkDerivation {
    name = "sa-fpga-tests";
    src = builtins.fetchGit {
      url = "git@gitlab-internal.bsc.es:hwdesign/rtl/core-tile/sa-fpga.git";
      rev = "720be4f1f5dd0ef963135992578be2ab55fb5537";
      ref = "main";
    };
    dontConfigure = true;
    patches = [
      #./patches/sa-fpga-crt.patch
      #./patches/sa-fpga-text-address.patch
      ./patches/sa-fpga-uart.patch
      ./patches/sa-fpga-plic-registers.patch
      ./patches/sa-fpga-add-plic-claim-test.patch
    ];
    buildPhase = ''
      cd fpga_core_bridge/simulator/tests/c_tests/
      make RISCV_PREFIX=riscv64-unknown-linux-musl-

      # Generate binary images to be loaded in memory
      for f in *.riscv; do
        # Don't copy 0x40000000 section
        $OBJCOPY -R .tohost -O binary $f $f.bin
      done
    '';
    installPhase = ''
      ls -lah
      make install install_dir=$out
      cp -a *.bin $out
    '';
    dontFixup = true;
    hardeningDisable = [ "all" ];
  };

  rbootrom = prev.pkgsStatic.stdenv.mkDerivation {
    name = "rbootrom";
    src = ./bootrom;
    dontConfigure = true;
    buildPhase = ''
      make
    '';
    installPhase = ''
      mkdir $out
      cp rbootrom.bin rbootrom.elf $out/
    '';
    dontFixup = true;
    hardeningDisable = [ "all" ];
  };
}