nixos-riscv/overlay.nix

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final: prev:
# Changes to packages from nixpkgs
{
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blis = ((prev.blis.override {
blas64 = true;
withArchitecture = "generic";
}).overrideAttrs (old: {
nativeBuildInputs = (old.nativeBuildInputs or []) ++ [
prev.buildPackages.gfortran
];
})).overrideDerivation (old : {
configureFlags = [
"--enable-cblas"
"--blas-int-size=64"
"--enable-threading=openmp"
#"--build=x86_64-unknown-linux-gnu"
#"--host=riscv64-unknown-linux-gnu"
"generic"
];
});
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riscv-tools = prev.pkgsStatic.stdenv.mkDerivation {
name = "riscv-tools";
src = ./tools;
makeFlags = [ "PREFIX=${placeholder "out"}" ];
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};
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bitstreams = builtins.fetchGit {
url = "git@bscpm03.bsc.es:rarias/bitstreams.git";
rev = "2f899627a226890c6f9820aa44e34c2ecea03faf";
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};
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# Baremetal tests for standalone FPGA
sa-fpga-tests = prev.pkgsStatic.stdenv.mkDerivation {
name = "sa-fpga-tests";
src = builtins.fetchGit {
url = "git@gitlab-internal.bsc.es:hwdesign/rtl/core-tile/sa-fpga.git";
rev = "afe0372413a94fff279ca5d5002c3e999ac8defb";
ref = "ft/sv_eirq";
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};
dontConfigure = true;
patches = [
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#./patches/sa-fpga-crt.patch
#./patches/sa-fpga-text-address.patch
./patches/sa-fpga-uart.patch
./patches/sa-fpga-plic-registers.patch
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];
buildPhase = ''
cd fpga_core_bridge/simulator/tests/c_tests/
make RISCV_PREFIX=riscv64-unknown-linux-musl-
# Generate binary images to be loaded in memory
for f in *.riscv; do
# Don't copy 0x40000000 section
$OBJCOPY -R .tohost -O binary $f $f.bin
done
'';
installPhase = ''
ls -lah
make install install_dir=$out
cp -a *.bin $out
'';
dontFixup = true;
hardeningDisable = [ "all" ];
};
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rbootrom = prev.pkgsStatic.stdenv.mkDerivation {
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name = "rbootrom";
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src = ./bootrom;
dontConfigure = true;
buildPhase = ''
make
'';
installPhase = ''
mkdir $out
cp rbootrom.bin rbootrom.elf $out/
'';
dontFixup = true;
hardeningDisable = [ "all" ];
};
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}