158e232520
Update journal
2024-09-04 10:48:48 +02:00
32a7b2f3b7
Enable ethernet node in DT
2024-09-03 16:58:28 +02:00
1620684b8e
Disable aux timer as OpenSBI now fails
2024-09-03 16:14:16 +02:00
fa6227928e
Enable aux timer and test uart in DT
2024-09-03 16:09:53 +02:00
3ee0933d7b
Add plictool to dump PLIC state
2024-09-03 15:59:04 +02:00
1aa899c8f0
Print md5 checksum in fpgactl
2024-09-03 14:59:29 +02:00
ee354156fe
Disable DHCP client
2024-09-02 10:21:01 +02:00
6802d867db
Remove debug from the bootcmd line
2024-08-31 02:22:53 +02:00
a463d88b76
Disable strace for the activation script
2024-08-31 02:22:53 +02:00
1c95d96519
Disable nscd daemon too
2024-08-30 23:08:44 +02:00
e02d5a3999
Autologin as root in case the user is not working
2024-08-30 22:02:59 +02:00
4d70cb33de
Use jitterentropy-rngd instead of haveged
2024-08-30 21:21:30 +02:00
7a77a3ba80
Enable haveged service
2024-08-30 20:41:12 +02:00
7573145dcc
Disable nscd call in activation script
2024-08-30 20:00:28 +02:00
10fb6d0a0a
Disable awk verification
...
It seems to be causing problems with the CI output log.
2024-08-30 19:06:54 +02:00
2bf9e94ca6
Build the full system in CI
2024-08-30 18:53:58 +02:00
ec70f54609
Prepare CI pipeline to boot NixOS
...
Increase the timeout to 30 minutes and load the rootfs
2024-08-30 18:37:15 +02:00
cd1c340a34
Disable preinit script
2024-08-30 18:21:33 +02:00
5a97c527f4
Don't redirect stage2 output
2024-08-30 18:17:41 +02:00
46d897a574
Use a custom stage2 script with strace
2024-08-30 17:31:52 +02:00
101aa1b352
Don't print machine mode interrupts
...
Get are getting a lot of machine mode interrupts, which should be
delegated to supervisor directly. Disable them for now as otherwise they
will flood the log.
2024-08-30 15:20:11 +02:00
a7c6a6f1e6
Add CLINT to device tree at 0x4010_0000
2024-08-30 15:10:46 +02:00
dce8b59061
Print interrupt type from mcause
2024-08-30 14:30:03 +02:00
d72b5ff5e9
Disable the CLINT for now
2024-08-30 14:17:55 +02:00
51ceb85d69
Print FDT before booting in U-Boot
2024-08-30 14:06:15 +02:00
1ede19807e
Increase boot timeout to 5 minutes
2024-08-30 13:46:33 +02:00
742ce37cec
Automatically load U-Boot environment on boot
2024-08-30 13:46:00 +02:00
8a123d93bf
Place environment in U-Boot
2024-08-30 13:03:46 +02:00
93014c68b8
Disable PLIC test for now
...
Let's focus on the rest of the boot process.
2024-08-30 11:35:32 +02:00
9abb28e9c5
Update journal
2024-08-29 18:21:10 +02:00
6be0f70c8d
Fix PLIC offsets for aux timer
2024-08-29 17:14:04 +02:00
58ddfd4720
Dump registers in baremetal plic supervisor test
2024-08-29 16:06:07 +02:00
13b9cd8692
Don't enable machine interrupts in delegation test
2024-08-29 15:06:30 +02:00
b7d4a10a14
Don't load an external bootrom
...
Unfortunalely the bootrom is included in the bitstream now.
2024-08-29 14:41:09 +02:00
2204a8ea56
Change load address delta to 0x6000_0000
2024-08-29 14:39:27 +02:00
ebcef525ba
Update bitstream to try to fix delegation (again)
2024-08-29 13:44:11 +02:00
5072f40a2f
Leave automatic allocation in fpgalogin1
2024-08-28 16:23:17 +02:00
65b91368d6
Update baremetal tests to sv_eirq branch
2024-08-28 10:19:58 +02:00
2e2ba5b996
Use test result to pass the tests
2024-08-27 14:37:15 +02:00
8b491f519b
Add trampoline scripts to CI
2024-08-26 17:58:03 +02:00
056f572ee9
Add CI pipeline
2024-08-26 15:22:31 +02:00
26754fa6e4
Update journal
2024-08-26 15:15:10 +02:00
2fc69ebfc0
Update bootrom gitignore
2024-08-23 21:22:22 +02:00
806023778b
Initialize UART in bootrom
...
Unless the UART is properly initialized, the console won't display any
message until a next stage intializes it (OpenSBI) and then we will
start to see messages after uploading the next bootroms.
Follows the OpenSBI initialization for the UART setting the baud rate to
115200 and assuming a clock of 50 MHz.
2024-08-23 18:13:48 +02:00
417a4d5c75
Set the _hang trap in mtvec
2024-08-23 16:46:40 +02:00
2dcb2ac209
Save return address before calling putchar
2024-08-23 16:46:29 +02:00
2371ac2fda
Switch to rbootrom
2024-08-23 16:06:21 +02:00
8272212769
Add custom bootrom
2024-08-23 16:06:21 +02:00
44de310116
Switch to ox_u55c_f6b4a076 bitstream
2024-08-23 16:06:21 +02:00
Rodrigo Arias Mallo
7b75cd2563
Add UART patch for FPGA in sa-fpga tests
2024-08-23 13:23:33 +02:00
