806023778b
Initialize UART in bootrom
...
Unless the UART is properly initialized, the console won't display any
message until a next stage intializes it (OpenSBI) and then we will
start to see messages after uploading the next bootroms.
Follows the OpenSBI initialization for the UART setting the baud rate to
115200 and assuming a clock of 50 MHz.
2024-08-23 18:13:48 +02:00
417a4d5c75
Set the _hang trap in mtvec
2024-08-23 16:46:40 +02:00
2dcb2ac209
Save return address before calling putchar
2024-08-23 16:46:29 +02:00
2371ac2fda
Switch to rbootrom
2024-08-23 16:06:21 +02:00
8272212769
Add custom bootrom
2024-08-23 16:06:21 +02:00
44de310116
Switch to ox_u55c_f6b4a076 bitstream
2024-08-23 16:06:21 +02:00
Rodrigo Arias Mallo
7b75cd2563
Add UART patch for FPGA in sa-fpga tests
2024-08-23 13:23:33 +02:00
Rodrigo Arias Mallo
9177f610a7
Add FPGA baremetal tests
2024-08-22 17:12:42 +02:00
Rodrigo Arias Mallo
ae379f7b9a
Enable machine mode interrupts
2024-08-21 12:29:52 +02:00
Rodrigo Arias Mallo
7091ca455c
Enable timer from supervisor
2024-08-21 12:28:17 +02:00
Rodrigo Arias Mallo
2c5f8a8ccf
Print registers in supervisor
2024-08-21 11:42:12 +02:00
Rodrigo Arias Mallo
706d858347
Claim aux timer interrupt
2024-08-21 11:39:45 +02:00
Rodrigo Arias Mallo
ea081176f7
Clear MIP before enabling interrupts
2024-08-21 10:20:11 +02:00
Rodrigo Arias Mallo
2f28f9268a
Enable machine interrupts
2024-08-21 10:13:45 +02:00
Rodrigo Arias Mallo
cc65500434
Use csr_set to set stvec
2024-08-21 10:12:41 +02:00
Rodrigo Arias Mallo
64cc2a982f
Clear MIP before enabling timer
2024-08-21 10:09:06 +02:00
Rodrigo Arias Mallo
90df8a3ccb
Add stvec trap
2024-08-21 10:03:19 +02:00
Rodrigo Arias Mallo
baf45e6749
Dump more registers in PLIC test
2024-08-21 09:53:39 +02:00
Rodrigo Arias Mallo
fd2b766760
Improve progress print
2024-08-21 09:39:00 +02:00
Rodrigo Arias Mallo
1faef5b452
Don't enable machine interrupt
2024-08-21 09:29:22 +02:00
Rodrigo Arias Mallo
b7287bd4df
Port supervisor PLIC test to OpenSBI
2024-08-21 09:25:07 +02:00
Rodrigo Arias Mallo
298595ba3c
Enable also MEIE and MIE
2024-08-21 08:16:14 +02:00
Rodrigo Arias Mallo
a858b3548e
Enable SIE in MSTATUS too
2024-08-21 08:08:13 +02:00
Rodrigo Arias Mallo
60631ec37f
Enable SEIE in MIE directly from machine mode
2024-08-21 08:00:31 +02:00
Rodrigo Arias Mallo
05eed3af94
Disable MEIE bit in MIE register
2024-08-21 07:56:17 +02:00
Rodrigo Arias Mallo
1419473a08
Dump machine registers in OpenSBI
2024-08-21 07:14:23 +02:00
Rodrigo Arias Mallo
62bd702929
Restore stvec to its original value
2024-08-21 06:24:42 +02:00
Rodrigo Arias Mallo
19dbb857c8
Enable MEIP in OpenSBI
2024-08-03 14:55:35 +02:00
Rodrigo Arias Mallo
91d3e9b163
Set stvec to zero
2024-08-02 16:13:46 +02:00
Rodrigo Arias Mallo
98f794e52d
Enable timer command in U-Boot
2024-08-02 15:27:20 +02:00
Rodrigo Arias Mallo
33fb07481a
Add exception enable U-Boot command
2024-08-02 13:49:12 +02:00
Rodrigo Arias Mallo
055f03980c
Add exception sregs command to U-Boot
2024-08-02 13:18:18 +02:00
Rodrigo Arias Mallo
995b1e3848
Delegate external interrupts to U-Boot
2024-08-02 12:15:47 +02:00
Rodrigo Arias Mallo
e67965cc0a
Always enable external machine mode interrupts
2024-08-02 10:33:31 +02:00
Rodrigo Arias Mallo
038d2e7156
Try opensbi without supervisor ext delegation
2024-08-01 20:22:57 +02:00
cd7eb7179f
Update journal with PLIC experiments
2024-08-01 19:29:49 +02:00
eee26f2b4d
More experiments with OpenSBI 1.5 with debug
2024-07-15 11:02:27 +02:00
9fac87a00e
Move FDT to 0xc0000000
2024-07-12 18:59:48 +02:00
8725d04533
Switch OpenSBI to generic
2024-07-12 18:53:16 +02:00
c38edfe737
Enable PLIC
2024-07-12 18:51:17 +02:00
fc7bfddd64
Switch to openpiton configuration
2024-07-12 18:47:48 +02:00
80c93613d2
Try FDT address 0x80013000
2024-07-12 18:40:39 +02:00
d3779d0f95
Revert serial address and move FDT
2024-07-12 18:28:43 +02:00
444bb635f6
Move serial to 0x4000_0000
2024-07-12 18:25:14 +02:00
bed3c7ba5c
Disable PLIC from DT
2024-07-12 18:19:58 +02:00
9a7b230b5b
Rollback to OpenSBI 1.4
2024-07-12 18:07:25 +02:00
384069130b
Reduce OpenSBI trap debug message
2024-07-12 17:50:22 +02:00
7d9f375e4a
Remove newline in OpenSBI trap debug line
2024-07-12 17:38:53 +02:00
c6e2db8c2d
Add extra debug messages
2024-07-12 16:36:18 +02:00
71c81f8dcd
Add debug in OpenSBI trap handler
2024-07-12 16:09:51 +02:00
