Prepare device tree to accomodate another UART
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27
ox-plic.dts
27
ox-plic.dts
@ -4,6 +4,12 @@
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#size-cells = <2>; /* 64 bits memory addresses */
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#size-cells = <2>; /* 64 bits memory addresses */
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compatible = "riscv,rv64i";
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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aliases {
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serial0 = &uart_console; // ttyS0
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serial1 = &uart_testing; // ttyS1
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};
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// chosen {
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// chosen {
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// bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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// bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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// };
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// };
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@ -86,14 +92,29 @@
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#size-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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ranges;
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ranges;
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SERIAL: serial@40001000 {
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/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
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* consoles */
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/* The serial for the kernel console */
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uart_console: serial@40001000 {
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compatible = "ns16550";
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compatible = "ns16550";
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reg = <0x0 0x40001000 0x0 0x1000>;
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reg = <0x0 0x40001000 0x0 0x1000>;
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reg-shift = <2>;
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/* No interrupts for this UART, use console=hvc0 */
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/* This clock is the SERIAL_CLK */
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clock-frequency = <25000000>;
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current-speed = <115200>;
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status = "okay";
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};
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/* The serial for interrupt tests */
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uart_testing: serial@40003000 {
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compatible = "ns16550";
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reg = <0x0 0x40003000 0x0 0x1000>;
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interrupts = <1>; /* Output interrupt 1 */
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interrupts = <1>; /* Output interrupt 1 */
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interrupt-parent = <&PLIC>;
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interrupt-parent = <&PLIC>;
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reg-shift = <2>;
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reg-shift = <2>;
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/* This clock is the SERIAL_CLK */
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clock-frequency = <25000000>;
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clock-frequency = <50000000>;
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current-speed = <115200>;
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current-speed = <115200>;
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status = "okay";
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status = "okay";
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};
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};
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