Reached working U-Boot prompt
The serial compatible string must be "ns16550" to be recognized by U-Boot.
This commit is contained in:
parent
72b4788888
commit
a8f3234031
@ -87,17 +87,22 @@
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nixpkgs.overlays = [ (final: prev: {
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nixpkgs.overlays = [ (final: prev: {
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ox-dtb = prev.runCommand "ox.dtb" {
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ox-dtb = prev.runCommand "ox.dtb" {
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dtsFile = ./ox-plic.dts;
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#dtsFile = ./xavi.dts;
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nativeBuildInputs = [ prev.buildPackages.dtc ];
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nativeBuildInputs = [ prev.buildPackages.dtc ];
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} "dtc -O dtb -o $out ${./ox-plic.dts}";
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} "dtc -O dtb -o $out $dtsFile";
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uboot = prev.ubootQemuRiscv64Smode.override {
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uboot = prev.ubootQemuRiscv64Smode.override {
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filesToInstall = [ "u-boot.bin" "u-boot-nodtb.bin" ];
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filesToInstall = [ "u-boot.bin" "u-boot-nodtb.bin" ];
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version = "2023.07.02-print-cpu-probe";
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version = "2023.07.02-print-cpu-probe";
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src = builtins.fetchGit {
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src = builtins.fetchGit {
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url = "file:///home/Computational/rarias/riscv/u-boot";
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url = "file:///home/Computational/rarias/riscv/u-boot";
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rev = "b0868e84c392daadcaf611f92209d0c82203386f";
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rev = "6fb984f14607c53878ba0ed82425d77e396b727b";
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};
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};
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#patches = [ ./u-boot-debug.patch ];
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#patches = [ ./u-boot-debug.patch ];
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#
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# CONFIG_SERIAL_PRESENT=n
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# CONFIG_SYS_NS16550=n
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extraConfig = ''
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extraConfig = ''
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CONFIG_RISCV_ISA_C=n
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CONFIG_RISCV_ISA_C=n
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CONFIG_REQUIRE_SERIAL_CONSOLE=n
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CONFIG_REQUIRE_SERIAL_CONSOLE=n
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@ -117,7 +122,6 @@
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_SBI_CONSOLE=y
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CONFIG_DEBUG_SBI_CONSOLE=y
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CONFIG_SYS_NS16550=n
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CONFIG_SMP=n
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CONFIG_SMP=n
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CONFIG_TRACE_EARLY=y
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CONFIG_TRACE_EARLY=y
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CONFIG_LOG=y
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CONFIG_LOG=y
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@ -183,7 +187,7 @@
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#"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
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#"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
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#"PLATFORM_RISCV_ABI=lp64d"
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#"PLATFORM_RISCV_ABI=lp64d"
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"FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin"
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"FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin"
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"FW_FDT_PATH=ox.dtb"
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"FW_FDT_PATH=${final.ox-dtb}"
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];
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];
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patches = [ ./ox-alveo-platform-plic.patch ];
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patches = [ ./ox-alveo-platform-plic.patch ];
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});
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});
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33
ox-plic.dts
33
ox-plic.dts
@ -3,7 +3,7 @@
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#address-cells = <0x00000002>;
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "riscv,rv64i";
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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chosen {
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chosen {
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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};
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};
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@ -11,7 +11,7 @@
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#address-cells = <0x00000001>;
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x0000c350>;
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timebase-frequency = <0x0000c350>;
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cpu@0 {
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CPU0: cpu@0 {
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clock-frequency = <0x02FAF080>;
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clock-frequency = <0x02FAF080>;
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device_type = "cpu";
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device_type = "cpu";
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reg = <0x00000000>;
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reg = <0x00000000>;
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@ -20,10 +20,12 @@
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riscv,isa = "rv64imafd";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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mmu-type = "riscv,sv39";
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tlb-split;
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tlb-split;
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phandle = <0x00000004>;
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L3: interrupt-controller {
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L3: interrupt-controller {
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#interrupt-cells = <0x00000001>;
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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compatible = "riscv,cpu-intc";
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phandle = <0x00000005>;
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};
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};
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};
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};
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};
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};
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@ -38,16 +40,19 @@
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eth_pool: dma_pool@60000000 {
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eth_pool: dma_pool@60000000 {
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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phandle = <0x00000001>;
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};
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};
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onic_pool: dma_pool@70000000 {
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onic_pool: dma_pool@70000000 {
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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compatible = "shared-dma-pool";
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phandle = <0x00000006>;
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};
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};
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};
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};
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eth0_clk: eth0_clk {
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eth0_clk: eth0_clk {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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clock-frequency = <0x09502f90>;
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phandle = <0x00000002>;
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};
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};
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pmem@1bff00000 {
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pmem@1bff00000 {
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volatile;
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volatile;
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@ -71,15 +76,16 @@
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#size-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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ranges;
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ranges;
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serial@40001000 {
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SERIAL: serial@40001000 {
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compatible = "ns16750";
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compatible = "ns16550";
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reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
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reg = <0x0 0x40001000 0x0 0x00000100>;
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interrupts = <0x00000000>;
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interrupts = <0>;
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port-number = <0x00000000>;
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/*port-number = <0>;*/
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reg-shift = <0x00000002>;
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reg-shift = <2>;
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clock-frequency = <0x02FAF080>;
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clock-frequency = <50000000>;
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current-speed = <0x0001c200>;
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current-speed = <115200>;
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status = "okay";
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status = "okay";
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phandle = <0x00000007>;
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};
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};
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ethernet0 {
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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xlnx,rxmem = <0x000005f2>;
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@ -124,7 +130,11 @@
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};
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};
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clint@40002000 {
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clint@40002000 {
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reg-names = "control";
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reg-names = "control";
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interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
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interrupts-extended =
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<&CPU0 0x3>, <&CPU0 0x7>,
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<&L3 0x3>, <&L3 0x7>,
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<&onic_pool 0x3>, <&onic_pool 0x7>,
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<&SERIAL 0x3>, <&SERIAL 0x7>;
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compatible = "riscv,clint0";
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compatible = "riscv,clint0";
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#interrupt-cells = <0x00000001>;
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#interrupt-cells = <0x00000001>;
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reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
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reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
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@ -137,6 +147,7 @@
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reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
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reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
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riscv,ndev = <0x00000003>;
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riscv,ndev = <0x00000003>;
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riscv,max-priority = <0x00000007>;
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riscv,max-priority = <0x00000007>;
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phandle = <0x00000003>;
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};
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};
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};
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};
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};
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};
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@ -1,278 +0,0 @@
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LOx$
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OpenSBI v1.2
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____ _____ ____ _____
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/ __ \ / ____| _ \_ _|
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| | | |_ __ ___ _ __ | (___ | |_) || |
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| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
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| |__| | |_) | __/ | | |____) | |_) || |_
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\____/| .__/ \___|_| |_|_____/|____/_____|
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Platform Name : Sargantana (for Xilinx Alveo FPGA)
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Platform Features : medeleg
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Platform HART Count : 1
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Platform IPI Device : ---
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Platform Timer Device : generic_timer @ 25000000Hz
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Platform Console Device : alveo_uart
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Platform HSM Device : ---
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Platform PMU Device : ---
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Platform Reboot Device : ---
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Platform Shutdown Device : ---
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Firmware Base : 0x80000000
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Firmware Size : 148 KB
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Runtime SBI Version : 1.0
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Domain0 Name : root
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Domain0 Boot HART : 0
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Domain0 HARTs : 0*
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Domain0 Region00 : 0x0000000080000000-0x000000008003ffff ()
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Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
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Domain0 Next Address : 0x0000000080200000
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Domain0 Next Arg1 : 0x0000000080010000
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Domain0 Next Mode : S-mode
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Domain0 SysReset : yes
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Boot HART ID : 0
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Boot HART Domain : root
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Boot HART Priv Version : v1.10
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Boot HART Base ISA : rv64imafdc
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Boot HART ISA Extensions : time
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Boot HART PMP Count : 0
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Boot HART PMP Granularity : 0
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Boot HART PMP Address Bits: 0
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Boot HART MHPM Count : 29
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Boot HART MIDELEG : 0x0000000000000222
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Boot HART MEDELEG : 0x000000000000b109
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<debug_uart>
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Core: 9 devices, 8 uclasses, devicetree: separate
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MMC:
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Loading Environment from <NULL>... OK
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In: serial@40001000
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Out: serial@40001000
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Err: serial@40001000
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Model: Barcelona Supercomputing Center - Lagarto Ox
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Hit any key to stop autoboot: 0
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LOx$ fdt
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fdt - flattened device tree utility commands
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Usage:
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fdt addr [-c] [-q] <addr> [<size>] - Set the [control] fdt location to <addr>
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fdt apply <addr> - Apply overlay to the DT
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fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active
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fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed
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fdt print <path> [<prop>] - Recursive print starting at <path>
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fdt list <path> [<prop>] - Print one level starting at <path>
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fdt get value <var> <path> <prop> [<index>] - Get <property> and store in <var>
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In case of stringlist property, use optional <index>
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to select string within the stringlist. Default is 0.
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fdt get name <var> <path> <index> - Get name of node <index> and store in <var>
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fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var>
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fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var>
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fdt set <path> <prop> [<val>] - Set <property> [to <val>]
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fdt mknode <path> <node> - Create a new node after <path>
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fdt rm <path> [<prop>] - Delete the node or <property>
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fdt header [get <var> <member>] - Display header info
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get - get header member <member> and store it in <var>
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fdt bootcpu <id> - Set boot cpuid
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fdt memory <addr> <size> - Add/Update memory node
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fdt rsvmem print - Show current mem reserves
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fdt rsvmem add <addr> <size> - Add a mem reserve
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fdt rsvmem delete <index> - Delete a mem reserves
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fdt chosen [<start> <size>] - Add/update the /chosen branch in the tree
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<start>/<size> - initrd start addr/size
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NOTE: Dereference aliases by omitting the leading '/', e.g. fdt print ethernet0.
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LOx$ fdt print
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No FDT memory address configured. Please configure
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the FDT address via "fdt addr <address>" command.
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Aborting!
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LOx$ fdt list
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No FDT memory address configured. Please configure
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the FDT address via "fdt addr <address>" command.
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Aborting!
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LOx$ printenv
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arch=riscv
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baudrate=115200
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board=riscv64
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board_name=riscv64
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bootcmd=fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; blkmap create pmem2; blkmap map pmem2 0 0x40000 mem 0x1b7f00000; blkmap info; ls blkmap 0; load blkmap 0 ${kernel_addr_r} Image; setenv bootargs ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash; booti ${kernel_addr_r} - ${fdt_addr_r};
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bootdelay=10
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cpu=generic
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fdt_addr_r=0x86000000
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fdtcontroladdr=e7d87e60
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image=boot/Image
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kernel_addr_r=0x80200000
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loadaddr=0x87000000
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mmcdev=0
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mmcpart=1
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stderr=serial@40001000
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stdin=serial@40001000
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stdout=serial@40001000
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vendor=openpiton
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Environment size: 640/126972 bytes
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LOx$ fdt addr ${fdt_addr_r}
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libfdt fdt_check_header(): FDT_ERR_BADMAGIC
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LOx$ fdt addr ${fdtcontroladdr}
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Working FDT set to e7d87e60
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LOx$ fdt print
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/ {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox";
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chosen {
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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};
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cpus {
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x0000c350>;
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cpu@0 {
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clock-frequency = <0x02faf080>;
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device_type = "cpu";
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reg = <0x00000000>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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phandle = <0x00000004>;
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interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x00000005>;
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
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};
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reserved-memory {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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ranges;
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dma_pool@60000000 {
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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phandle = <0x00000001>;
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};
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dma_pool@70000000 {
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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phandle = <0x00000006>;
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};
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};
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eth0_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
|
|
||||||
clock-frequency = <0x09502f90>;
|
|
||||||
phandle = <0x00000002>;
|
|
||||||
};
|
|
||||||
pmem@1bff00000 {
|
|
||||||
volatile;
|
|
||||||
compatible = "pmem-region";
|
|
||||||
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
|
|
||||||
};
|
|
||||||
pmem2@1b7f00000 {
|
|
||||||
#address-cells = <0x00000002>;
|
|
||||||
#size-cells = <0x00000002>;
|
|
||||||
volatile;
|
|
||||||
compatible = "pmem-region";
|
|
||||||
reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
|
|
||||||
};
|
|
||||||
pmem3@f7e00000 {
|
|
||||||
volatile;
|
|
||||||
compatible = "pmem-region";
|
|
||||||
reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
|
|
||||||
};
|
|
||||||
soc {
|
|
||||||
#address-cells = <0x00000002>;
|
|
||||||
#size-cells = <0x00000002>;
|
|
||||||
compatible = "BSC,Lagarto-bare-soc", "simple-bus";
|
|
||||||
ranges;
|
|
||||||
serial@40001000 {
|
|
||||||
compatible = "ns16750";
|
|
||||||
reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
|
|
||||||
interrupts = <0x00000000>;
|
|
||||||
port-number = <0x00000000>;
|
|
||||||
reg-shift = <0x00000002>;
|
|
||||||
clock-frequency = <0x017d7840>;
|
|
||||||
current-speed = <0x0001c200>;
|
|
||||||
status = "okay";
|
|
||||||
phandle = <0x00000007>;
|
|
||||||
};
|
|
||||||
ethernet0 {
|
|
||||||
xlnx,rxmem = <0x000005f2>;
|
|
||||||
carv,mtu = <0x000005dc>;
|
|
||||||
carv,no-mac;
|
|
||||||
device_type = "network";
|
|
||||||
local-mac-address = [02 05 00 01 00 05];
|
|
||||||
axistream-connected = <0x000000fe>;
|
|
||||||
compatible = "xlnx,xxv-ethernet-1.0-carv";
|
|
||||||
memory-region = <0x00000001>;
|
|
||||||
};
|
|
||||||
dma@40020000 {
|
|
||||||
xlnx,include-dre;
|
|
||||||
phandle = <0x000000fe>;
|
|
||||||
#dma-cells = <0x00000001>;
|
|
||||||
compatible = "xlnx,axi-dma-1.00.a";
|
|
||||||
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
|
|
||||||
clocks = <0x00000002 0x00000002 0x00000002 0x00000002>;
|
|
||||||
reg = <0x00000000 0x40200000 0x00000000 0x00400000>;
|
|
||||||
interrupt-names = "mm2s_introut", "s2mm_introut";
|
|
||||||
interrupt-parent = <0x00000003>;
|
|
||||||
interrupts = <0x00000002 0x00000003>;
|
|
||||||
xlnx,addrwidth = <0x00000028>;
|
|
||||||
xlnx,include-sg;
|
|
||||||
xlnx,sg-length-width = <0x00000017>;
|
|
||||||
dma-channel@40020000 {
|
|
||||||
compatible = "xlnx,axi-dma-mm2s-channel";
|
|
||||||
dma-channels = <0x00000001>;
|
|
||||||
interrupts = <0x00000002>;
|
|
||||||
xlnx,datawidth = <0x00000040>;
|
|
||||||
xlnx,device-id = <0x00000000>;
|
|
||||||
xlnx,include-dre;
|
|
||||||
};
|
|
||||||
dma-channel@40020030 {
|
|
||||||
compatible = "xlnx,axi-dma-s2mm-channel";
|
|
||||||
dma-channels = <0x00000001>;
|
|
||||||
interrupts = <0x00000003>;
|
|
||||||
xlnx,datawidth = <0x00000040>;
|
|
||||||
xlnx,device-id = <0x00000000>;
|
|
||||||
xlnx,include-dre;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
clint@40002000 {
|
|
||||||
reg-names = "control";
|
|
||||||
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
|
|
||||||
compatible = "riscv,clint0";
|
|
||||||
#interrupt-cells = <0x00000001>;
|
|
||||||
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
|
|
||||||
};
|
|
||||||
plic@fff1100000 {
|
|
||||||
#address-cells = <0x00000000>;
|
|
||||||
compatible = "riscv,plic0";
|
|
||||||
#interrupt-cells = <0x00000001>;
|
|
||||||
reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
|
|
||||||
riscv,ndev = <0x00000003>;
|
|
||||||
riscv,max-priority = <0x00000007>;
|
|
||||||
interrupt-controller;
|
|
||||||
phandle = <0x00000003>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
__symbols__ {
|
|
||||||
CPU0 = "/cpus/cpu@0";
|
|
||||||
CPU0_intc = "/cpus/cpu@0/interrupt-controller";
|
|
||||||
eth_pool = "/reserved-memory/dma_pool@60000000";
|
|
||||||
meep_pool = "/reserved-memory/dma_pool@70000000";
|
|
||||||
eth0_clk = "/eth0_clk";
|
|
||||||
uart0 = "/soc/serial@40001000";
|
|
||||||
dma_eth = "/soc/dma@40020000";
|
|
||||||
PLIC0 = "/soc/plic@fff1100000";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
LOx$
|
|
||||||
159
xavi.dts
Normal file
159
xavi.dts
Normal file
@ -0,0 +1,159 @@
|
|||||||
|
/dts-v1/;
|
||||||
|
/ {
|
||||||
|
#address-cells = <0x00000002>;
|
||||||
|
#size-cells = <0x00000002>;
|
||||||
|
compatible = "riscv,rv64i";
|
||||||
|
model = "Barcelona Supercomputing Center - Lagarto Ox";
|
||||||
|
chosen {
|
||||||
|
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
|
||||||
|
};
|
||||||
|
cpus {
|
||||||
|
#address-cells = <0x00000001>;
|
||||||
|
#size-cells = <0x00000000>;
|
||||||
|
timebase-frequency = <0x0000c350>;
|
||||||
|
cpu@0 {
|
||||||
|
clock-frequency = <0x02faf080>;
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0x00000000>;
|
||||||
|
status = "okay";
|
||||||
|
compatible = "riscv";
|
||||||
|
riscv,isa = "rv64imafd";
|
||||||
|
mmu-type = "riscv,sv39";
|
||||||
|
tlb-split;
|
||||||
|
phandle = <0x00000004>;
|
||||||
|
interrupt-controller {
|
||||||
|
#interrupt-cells = <0x00000001>;
|
||||||
|
interrupt-controller;
|
||||||
|
compatible = "riscv,cpu-intc";
|
||||||
|
phandle = <0x00000005>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
memory@80000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
|
||||||
|
};
|
||||||
|
reserved-memory {
|
||||||
|
#address-cells = <0x00000002>;
|
||||||
|
#size-cells = <0x00000002>;
|
||||||
|
ranges;
|
||||||
|
dma_pool@60000000 {
|
||||||
|
reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
|
||||||
|
compatible = "shared-dma-pool";
|
||||||
|
phandle = <0x00000001>;
|
||||||
|
};
|
||||||
|
dma_pool@70000000 {
|
||||||
|
reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
|
||||||
|
compatible = "shared-dma-pool";
|
||||||
|
phandle = <0x00000006>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
eth0_clk {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0x00000000>;
|
||||||
|
clock-frequency = <0x09502f90>;
|
||||||
|
phandle = <0x00000002>;
|
||||||
|
};
|
||||||
|
pmem@1bff00000 {
|
||||||
|
volatile;
|
||||||
|
compatible = "pmem-region";
|
||||||
|
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
|
||||||
|
};
|
||||||
|
pmem2@1b7f00000 {
|
||||||
|
#address-cells = <0x00000002>;
|
||||||
|
#size-cells = <0x00000002>;
|
||||||
|
volatile;
|
||||||
|
compatible = "pmem-region";
|
||||||
|
reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
|
||||||
|
};
|
||||||
|
pmem3@f7e00000 {
|
||||||
|
volatile;
|
||||||
|
compatible = "pmem-region";
|
||||||
|
reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
|
||||||
|
};
|
||||||
|
soc {
|
||||||
|
#address-cells = <0x00000002>;
|
||||||
|
#size-cells = <0x00000002>;
|
||||||
|
compatible = "BSC,Lagarto-bare-soc", "simple-bus";
|
||||||
|
ranges;
|
||||||
|
serial@40001000 {
|
||||||
|
compatible = "ns16750";
|
||||||
|
reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
|
||||||
|
interrupts = <0x00000000>;
|
||||||
|
port-number = <0x00000000>;
|
||||||
|
reg-shift = <0x00000002>;
|
||||||
|
clock-frequency = <0x017d7840>;
|
||||||
|
current-speed = <0x0001c200>;
|
||||||
|
status = "okay";
|
||||||
|
phandle = <0x00000007>;
|
||||||
|
};
|
||||||
|
ethernet0 {
|
||||||
|
xlnx,rxmem = <0x000005f2>;
|
||||||
|
carv,mtu = <0x000005dc>;
|
||||||
|
carv,no-mac;
|
||||||
|
device_type = "network";
|
||||||
|
local-mac-address = [02 05 00 01 00 05];
|
||||||
|
axistream-connected = <0x000000fe>;
|
||||||
|
compatible = "xlnx,xxv-ethernet-1.0-carv";
|
||||||
|
memory-region = <0x00000001>;
|
||||||
|
};
|
||||||
|
dma@40020000 {
|
||||||
|
xlnx,include-dre;
|
||||||
|
phandle = <0x000000fe>;
|
||||||
|
#dma-cells = <0x00000001>;
|
||||||
|
compatible = "xlnx,axi-dma-1.00.a";
|
||||||
|
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
|
||||||
|
clocks = <0x00000002 0x00000002 0x00000002 0x00000002>;
|
||||||
|
reg = <0x00000000 0x40200000 0x00000000 0x00400000>;
|
||||||
|
interrupt-names = "mm2s_introut", "s2mm_introut";
|
||||||
|
interrupt-parent = <0x00000003>;
|
||||||
|
interrupts = <0x00000002 0x00000003>;
|
||||||
|
xlnx,addrwidth = <0x00000028>;
|
||||||
|
xlnx,include-sg;
|
||||||
|
xlnx,sg-length-width = <0x00000017>;
|
||||||
|
dma-channel@40020000 {
|
||||||
|
compatible = "xlnx,axi-dma-mm2s-channel";
|
||||||
|
dma-channels = <0x00000001>;
|
||||||
|
interrupts = <0x00000002>;
|
||||||
|
xlnx,datawidth = <0x00000040>;
|
||||||
|
xlnx,device-id = <0x00000000>;
|
||||||
|
xlnx,include-dre;
|
||||||
|
};
|
||||||
|
dma-channel@40020030 {
|
||||||
|
compatible = "xlnx,axi-dma-s2mm-channel";
|
||||||
|
dma-channels = <0x00000001>;
|
||||||
|
interrupts = <0x00000003>;
|
||||||
|
xlnx,datawidth = <0x00000040>;
|
||||||
|
xlnx,device-id = <0x00000000>;
|
||||||
|
xlnx,include-dre;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
clint@40002000 {
|
||||||
|
reg-names = "control";
|
||||||
|
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
|
||||||
|
compatible = "riscv,clint0";
|
||||||
|
#interrupt-cells = <0x00000001>;
|
||||||
|
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
|
||||||
|
};
|
||||||
|
plic@fff1100000 {
|
||||||
|
#address-cells = <0x00000000>;
|
||||||
|
compatible = "riscv,plic0";
|
||||||
|
#interrupt-cells = <0x00000001>;
|
||||||
|
reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
|
||||||
|
riscv,ndev = <0x00000003>;
|
||||||
|
riscv,max-priority = <0x00000007>;
|
||||||
|
interrupt-controller;
|
||||||
|
phandle = <0x00000003>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
__symbols__ {
|
||||||
|
CPU0 = "/cpus/cpu@0";
|
||||||
|
CPU0_intc = "/cpus/cpu@0/interrupt-controller";
|
||||||
|
eth_pool = "/reserved-memory/dma_pool@60000000";
|
||||||
|
meep_pool = "/reserved-memory/dma_pool@70000000";
|
||||||
|
eth0_clk = "/eth0_clk";
|
||||||
|
uart0 = "/soc/serial@40001000";
|
||||||
|
dma_eth = "/soc/dma@40020000";
|
||||||
|
PLIC0 = "/soc/plic@fff1100000";
|
||||||
|
};
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue
Block a user