Clean DTS
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16ee113cb8
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@ -195,25 +195,10 @@
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interrupt-controller; /* Receives interrupts */
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interrupt-controller; /* Receives interrupts */
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#address-cells = <0>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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#interrupt-cells = <1>;
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/* Sends interrupts to HART interrupt controllers */
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/* Sends interrupts to HART interrupt controllers.
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* Configures two output targets or contexts:
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/*
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* - context 0: machine mode external interrupt (11)
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* From: linux-6.6.1/arch/riscv/include/asm/csr.h
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* - context 1: supervisor mode external interrupt (9)
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*
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* Interrupt causes (minus the high bit)
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* #define IRQ_S_SOFT 1
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* #define IRQ_VS_SOFT 2
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* #define IRQ_M_SOFT 3
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* #define IRQ_S_TIMER 5
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* #define IRQ_VS_TIMER 6
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* #define IRQ_M_TIMER 7
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* #define IRQ_S_EXT 9
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* #define IRQ_VS_EXT 10
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* #define IRQ_M_EXT 11
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* #define IRQ_S_GEXT 12
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* #define IRQ_PMU_OVF 13
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* #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
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* #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
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*/
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*/
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interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
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interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
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reg = < 0x0 0x40800000 0x0 0x00400000>;
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reg = < 0x0 0x40800000 0x0 0x00400000>;
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@ -236,38 +221,19 @@
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interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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compatible = "riscv,clint0";
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compatible = "riscv,clint0";
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};
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};
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// aux_timer: clint@40010000 {
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// reg = <0x0 0x40010000 0x0 0x00010000>;
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// reg-names = "control";
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// interrupts = <4>; /* PLIC input source 4 */
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// interrupt-parent = <&PLIC>;
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// compatible = "riscv,clint0";
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// };
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// clint: clint@40002000 {
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// /* MTIME and MTIMECMP address and size pairs */
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// reg = <0x0 0x40002000 0x0 0x8>, <0x0 0x40002008 0x0 0x8>;
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// interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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// /*<&CPU0 0x3>, <&CPU0 0x7>,*/
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// /*<&onic_pool 0x3>, <&onic_pool 0x7>,*/
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// /*<&SERIAL 0x3>, <&SERIAL 0x7>*/
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//
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// /* Allows using the "generic" platform in OpenSBI. */
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// compatible = "riscv,aclint-mtimer";
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// };
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/* Guesswork: There must be a timer at 0x40170000 as it is
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* initialized in OpenSBI. It seems to drive the console. */
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//SERIAL_CLK: timer@40170000 {
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// clock-frequency = <100000000>;
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// clocks = <&clk_bus_0>;
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// compatible = "xlnx,xps-timer-1.00.a";
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// interrupt-parent = <&axi_intc_1>;
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// interrupts = <2 2>;
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// reg = <0x41c00000 0x10000>;
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// xlnx,count-width = <0x20>;
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// xlnx,one-timer-only = <0x0>;
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//};
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/* There is another auxiliar clint (timer) at 40010000 for
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* tests, but we don't tell the kernel so we can use it for
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* testing interrupts manually. */
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#if 0
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aux_timer: clint@40010000 {
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reg = <0x0 0x40010000 0x0 0x00010000>;
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reg-names = "control";
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interrupts = <4>; /* PLIC input source 4 */
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interrupt-parent = <&PLIC>;
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compatible = "riscv,clint0";
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};
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#endif
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#ifdef ENABLE_SPI
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#ifdef ENABLE_SPI
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uart16750: serial@40005000 {
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uart16750: serial@40005000 {
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