diff --git a/dts/lagarto_ox.dts b/dts/lagarto_ox.dts index 1c0ea21..df93255 100644 --- a/dts/lagarto_ox.dts +++ b/dts/lagarto_ox.dts @@ -195,25 +195,10 @@ interrupt-controller; /* Receives interrupts */ #address-cells = <0>; #interrupt-cells = <1>; - /* Sends interrupts to HART interrupt controllers */ - - /* - * From: linux-6.6.1/arch/riscv/include/asm/csr.h - * - * Interrupt causes (minus the high bit) - * #define IRQ_S_SOFT 1 - * #define IRQ_VS_SOFT 2 - * #define IRQ_M_SOFT 3 - * #define IRQ_S_TIMER 5 - * #define IRQ_VS_TIMER 6 - * #define IRQ_M_TIMER 7 - * #define IRQ_S_EXT 9 - * #define IRQ_VS_EXT 10 - * #define IRQ_M_EXT 11 - * #define IRQ_S_GEXT 12 - * #define IRQ_PMU_OVF 13 - * #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) - * #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) + /* Sends interrupts to HART interrupt controllers. + * Configures two output targets or contexts: + * - context 0: machine mode external interrupt (11) + * - context 1: supervisor mode external interrupt (9) */ interrupts-extended = <&HLIC0 11>, <&HLIC0 9>; reg = < 0x0 0x40800000 0x0 0x00400000>; @@ -236,38 +221,19 @@ interrupts-extended = <&HLIC0 3>, <&HLIC0 7>; compatible = "riscv,clint0"; }; -// aux_timer: clint@40010000 { -// reg = <0x0 0x40010000 0x0 0x00010000>; -// reg-names = "control"; -// interrupts = <4>; /* PLIC input source 4 */ -// interrupt-parent = <&PLIC>; -// compatible = "riscv,clint0"; -// }; -// clint: clint@40002000 { -// /* MTIME and MTIMECMP address and size pairs */ -// reg = <0x0 0x40002000 0x0 0x8>, <0x0 0x40002008 0x0 0x8>; -// interrupts-extended = <&HLIC0 3>, <&HLIC0 7>; -// /*<&CPU0 0x3>, <&CPU0 0x7>,*/ -// /*<&onic_pool 0x3>, <&onic_pool 0x7>,*/ -// /*<&SERIAL 0x3>, <&SERIAL 0x7>*/ -// -// /* Allows using the "generic" platform in OpenSBI. */ -// compatible = "riscv,aclint-mtimer"; -// }; - - /* Guesswork: There must be a timer at 0x40170000 as it is - * initialized in OpenSBI. It seems to drive the console. */ - //SERIAL_CLK: timer@40170000 { - // clock-frequency = <100000000>; - // clocks = <&clk_bus_0>; - // compatible = "xlnx,xps-timer-1.00.a"; - // interrupt-parent = <&axi_intc_1>; - // interrupts = <2 2>; - // reg = <0x41c00000 0x10000>; - // xlnx,count-width = <0x20>; - // xlnx,one-timer-only = <0x0>; - //}; + /* There is another auxiliar clint (timer) at 40010000 for + * tests, but we don't tell the kernel so we can use it for + * testing interrupts manually. */ + #if 0 + aux_timer: clint@40010000 { + reg = <0x0 0x40010000 0x0 0x00010000>; + reg-names = "control"; + interrupts = <4>; /* PLIC input source 4 */ + interrupt-parent = <&PLIC>; + compatible = "riscv,clint0"; + }; + #endif #ifdef ENABLE_SPI uart16750: serial@40005000 {