nixos-riscv/uboot-debug-ext-interrupts.patch
2024-08-02 12:15:47 +02:00

32 lines
989 B
Diff

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6cecadfac5..f649844b23 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -81,7 +81,7 @@ _start:
#if CONFIG_IS_ENABLED(RISCV_MMODE)
li t0, MIE_MSIE
#else
- li t0, SIE_SSIE
+ li t0, (SIE_SSIE + SIE_SEIE + SIE_STIE)
#endif
csrs MODE_PREFIX(ie), t0
#endif
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index a26ccc721f..b8d2a71223 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -193,10 +193,13 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
+ printf("u-boot: got ext interrupt %lu\n", irq);
+ show_regs(regs);
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
case IRQ_S_TIMER:
+ printf("u-boot: got timer interrupt %lu\n", irq);
timer_interrupt(0); /* handle timer interrupt */
break;
default: