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Clear MIP before enabling interrupts

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This commit is contained in:
Rodrigo Arias Mallo 2024-08-21 10:20:11 +02:00
parent 2f28f9268a
commit ea081176f7
1 changed files with 5 additions and 5 deletions
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10
opensbi-test-plic.patch
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@ -1,5 +1,5 @@
diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c
index 0ae604a..000b89c 100644
index 0ae604a..31d8082 100644
--- a/lib/sbi/sbi_irqchip.c
+++ b/lib/sbi/sbi_irqchip.c
@@ -9,6 +9,9 @@
@ -154,16 +154,16 @@ index 0ae604a..000b89c 100644
+
+ sbi_printf("Timer enabled in PLIC\n");
+
+ /* Enable external timer interrupts */
+ csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
+ csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
+
+ /*
+ * Clear mip CSR before proceeding with init to avoid any spurious
+ * external interrupts in S-mode.
+ */
+ csr_write(CSR_MIP, 0);
+
+ /* Enable external timer interrupts */
+ csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
+ csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
+
+ /* Enable timer interrupt */
+ *mtimecmp = *mtime + 10000;
+