From ea081176f74751aee73bc4ee8055b4608f443a27 Mon Sep 17 00:00:00 2001 From: Rodrigo Arias Mallo Date: Wed, 21 Aug 2024 10:20:11 +0200 Subject: [PATCH] Clear MIP before enabling interrupts --- opensbi-test-plic.patch | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/opensbi-test-plic.patch b/opensbi-test-plic.patch index 3bd6ba3..4697f00 100644 --- a/opensbi-test-plic.patch +++ b/opensbi-test-plic.patch @@ -1,5 +1,5 @@ diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c -index 0ae604a..000b89c 100644 +index 0ae604a..31d8082 100644 --- a/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c @@ -9,6 +9,9 @@ @@ -154,16 +154,16 @@ index 0ae604a..000b89c 100644 + + sbi_printf("Timer enabled in PLIC\n"); + -+ /* Enable external timer interrupts */ -+ csr_set(CSR_MIE, MIE_MEIE); /* Needed? */ -+ csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */ -+ + /* + * Clear mip CSR before proceeding with init to avoid any spurious + * external interrupts in S-mode. + */ + csr_write(CSR_MIP, 0); + ++ /* Enable external timer interrupts */ ++ csr_set(CSR_MIE, MIE_MEIE); /* Needed? */ ++ csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */ ++ + /* Enable timer interrupt */ + *mtimecmp = *mtime + 10000; +