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Enable PLIC

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This commit is contained in:
Rodrigo Arias 2024-07-12 18:51:17 +02:00
parent fc7bfddd64
commit c38edfe737
2 changed files with 33 additions and 31 deletions
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2
JOURNAL.md
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@ -2548,3 +2548,5 @@ With 0x80013000 we seem to enter OpenSBI code region.
Let's try with openpiton again, without the FDT address. We should disable the Let's try with openpiton again, without the FDT address. We should disable the
secondary console from the DT too. secondary console from the DT too.
No output, lets enable the PLIC again in the DT.

62
ox-plic.dts
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@ -184,37 +184,37 @@
/* Platform-Level Interrupt Controller: Delivers interrupts to /* Platform-Level Interrupt Controller: Delivers interrupts to
* HARTs. */ * HARTs. */
// PLIC: plic@40800000 { PLIC: plic@40800000 {
// compatible = "riscv,plic0"; compatible = "riscv,plic0";
// interrupt-controller; /* Receives interrupts */ interrupt-controller; /* Receives interrupts */
// #address-cells = <0>; #address-cells = <0>;
// #interrupt-cells = <1>; #interrupt-cells = <1>;
// /* Sends interrupts to HART interrupt controllers */ /* Sends interrupts to HART interrupt controllers */
//
// /* /*
// * From: linux-6.6.1/arch/riscv/include/asm/csr.h * From: linux-6.6.1/arch/riscv/include/asm/csr.h
// * *
// * Interrupt causes (minus the high bit) * Interrupt causes (minus the high bit)
// * #define IRQ_S_SOFT 1 * #define IRQ_S_SOFT 1
// * #define IRQ_VS_SOFT 2 * #define IRQ_VS_SOFT 2
// * #define IRQ_M_SOFT 3 * #define IRQ_M_SOFT 3
// * #define IRQ_S_TIMER 5 * #define IRQ_S_TIMER 5
// * #define IRQ_VS_TIMER 6 * #define IRQ_VS_TIMER 6
// * #define IRQ_M_TIMER 7 * #define IRQ_M_TIMER 7
// * #define IRQ_S_EXT 9 * #define IRQ_S_EXT 9
// * #define IRQ_VS_EXT 10 * #define IRQ_VS_EXT 10
// * #define IRQ_M_EXT 11 * #define IRQ_M_EXT 11
// * #define IRQ_S_GEXT 12 * #define IRQ_S_GEXT 12
// * #define IRQ_PMU_OVF 13 * #define IRQ_PMU_OVF 13
// * #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) * #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
// * #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) * #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
// */ */
// interrupts-extended = <&HLIC0 11>, <&HLIC0 9>; interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
// reg = < 0x0 0x40800000 0x0 0x00400000>; reg = < 0x0 0x40800000 0x0 0x00400000>;
// riscv,ndev = <3>; riscv,ndev = <3>;
// //riscv,max-priority = <0x7>; //riscv,max-priority = <0x7>;
// phandle = <0x3>; phandle = <0x3>;
// }; };
/* Core Local Interruptor: It directly connects to the timer and /* Core Local Interruptor: It directly connects to the timer and
* inter-processor interrupt lines of various HARTs (or CPUs) so * inter-processor interrupt lines of various HARTs (or CPUs) so
* RISC-V per-HART (or per-CPU) local interrupt controller is * RISC-V per-HART (or per-CPU) local interrupt controller is