From c38edfe737aa04e529aa7fc9099c708c2e659e8a Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
Date: Fri, 12 Jul 2024 18:51:17 +0200
Subject: [PATCH] Enable PLIC

---
 JOURNAL.md  |  2 ++
 ox-plic.dts | 62 ++++++++++++++++++++++++++---------------------------
 2 files changed, 33 insertions(+), 31 deletions(-)

diff --git a/JOURNAL.md b/JOURNAL.md
index 4e69a0f..ffab2fc 100644
--- a/JOURNAL.md
+++ b/JOURNAL.md
@@ -2548,3 +2548,5 @@ With 0x80013000 we seem to enter OpenSBI code region.
 
 Let's try with openpiton again, without the FDT address. We should disable the
 secondary console from the DT too.
+
+No output, lets enable the PLIC again in the DT.
diff --git a/ox-plic.dts b/ox-plic.dts
index 6e21697..e0191f4 100644
--- a/ox-plic.dts
+++ b/ox-plic.dts
@@ -184,37 +184,37 @@
 
 		/* Platform-Level Interrupt Controller: Delivers interrupts to
 		 * HARTs. */
-//		PLIC: plic@40800000 {
-//			compatible = "riscv,plic0";
-//			interrupt-controller; /* Receives interrupts */
-//			#address-cells = <0>;
-//			#interrupt-cells = <1>;
-//			/* Sends interrupts to HART interrupt controllers */
-//
-//			/*
-//			 * From: linux-6.6.1/arch/riscv/include/asm/csr.h
-//			 *
-//			 * Interrupt causes (minus the high bit)
-//			 * #define IRQ_S_SOFT      1
-//			 * #define IRQ_VS_SOFT     2
-//			 * #define IRQ_M_SOFT      3
-//			 * #define IRQ_S_TIMER     5
-//			 * #define IRQ_VS_TIMER    6
-//			 * #define IRQ_M_TIMER     7
-//			 * #define IRQ_S_EXT       9
-//			 * #define IRQ_VS_EXT      10
-//			 * #define IRQ_M_EXT       11
-//			 * #define IRQ_S_GEXT      12
-//			 * #define IRQ_PMU_OVF     13
-//			 * #define IRQ_LOCAL_MAX   (IRQ_PMU_OVF + 1)
-//			 * #define IRQ_LOCAL_MASK  GENMASK((IRQ_LOCAL_MAX - 1), 0)
-//			 */
-//			interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
-//			reg = < 0x0 0x40800000 0x0 0x00400000>;
-//			riscv,ndev = <3>;
-//			//riscv,max-priority = <0x7>;
-//			phandle = <0x3>;
-//		};
+		PLIC: plic@40800000 {
+			compatible = "riscv,plic0";
+			interrupt-controller; /* Receives interrupts */
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			/* Sends interrupts to HART interrupt controllers */
+
+			/*
+			 * From: linux-6.6.1/arch/riscv/include/asm/csr.h
+			 *
+			 * Interrupt causes (minus the high bit)
+			 * #define IRQ_S_SOFT      1
+			 * #define IRQ_VS_SOFT     2
+			 * #define IRQ_M_SOFT      3
+			 * #define IRQ_S_TIMER     5
+			 * #define IRQ_VS_TIMER    6
+			 * #define IRQ_M_TIMER     7
+			 * #define IRQ_S_EXT       9
+			 * #define IRQ_VS_EXT      10
+			 * #define IRQ_M_EXT       11
+			 * #define IRQ_S_GEXT      12
+			 * #define IRQ_PMU_OVF     13
+			 * #define IRQ_LOCAL_MAX   (IRQ_PMU_OVF + 1)
+			 * #define IRQ_LOCAL_MASK  GENMASK((IRQ_LOCAL_MAX - 1), 0)
+			 */
+			interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
+			reg = < 0x0 0x40800000 0x0 0x00400000>;
+			riscv,ndev = <3>;
+			//riscv,max-priority = <0x7>;
+			phandle = <0x3>;
+		};
 		/* Core Local Interruptor: It directly connects to the timer and
 		 * inter-processor interrupt lines of various HARTs (or CPUs) so
 		 * RISC-V per-HART (or per-CPU) local interrupt controller is