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Reached U-Boot console with FDT parsing error

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This commit is contained in:
Rodrigo Arias 2024-06-27 16:08:30 +02:00
parent 1bfc32e91a
commit 72b4788888
5 changed files with 506 additions and 119 deletions
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33
lagarto-ox.nix
View File

@ -86,14 +86,30 @@
}; };
nixpkgs.overlays = [ (final: prev: { nixpkgs.overlays = [ (final: prev: {
ox-dtb = prev.runCommand "ox.dtb" {
nativeBuildInputs = [ prev.buildPackages.dtc ];
} "dtc -O dtb -o $out ${./ox-plic.dts}";
uboot = prev.ubootQemuRiscv64Smode.override { uboot = prev.ubootQemuRiscv64Smode.override {
filesToInstall = [ "u-boot.bin" "u-boot-nodtb.bin" ]; filesToInstall = [ "u-boot.bin" "u-boot-nodtb.bin" ];
version = "2023.07.02-print-cpu-probe";
src = builtins.fetchGit {
url = "file:///home/Computational/rarias/riscv/u-boot";
rev = "b0868e84c392daadcaf611f92209d0c82203386f";
};
#patches = [ ./u-boot-debug.patch ];
extraConfig = '' extraConfig = ''
CONFIG_RISCV_ISA_C=n CONFIG_RISCV_ISA_C=n
CONFIG_REQUIRE_SERIAL_CONSOLE=n CONFIG_REQUIRE_SERIAL_CONSOLE=n
CONFIG_SERIAL_SEARCH_ALL=y CONFIG_SERIAL=y
CONFIG_SERIAL_PUTS=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_SHOW_REGS=y
CONFIG_LIBCOMMON_SUPPORT=y
CONFIG_SERIAL_SEARCH_ALL=n
CONFIG_SERIAL_PROBE_ALL=n
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD=y CONFIG_OF_EMBED=y
CONFIG_OF_HAS_PRIOR_STAGE=y CONFIG_OF_HAS_PRIOR_STAGE=y
CONFIG_BLKMAP=y CONFIG_BLKMAP=y
CONFIG_CMD_BLKMAP=y CONFIG_CMD_BLKMAP=y
@ -101,7 +117,18 @@
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_SBI_CONSOLE=y CONFIG_DEBUG_SBI_CONSOLE=y
CONFIG_SYS_NS16550=n
CONFIG_SMP=n
CONFIG_TRACE_EARLY=y
CONFIG_LOG=y
CONFIG_LOGLEVEL=9
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=9
''; '';
extraMakeFlags = [
"KCPPFLAGS=-DLOG_DEBUG"
#"EXT_DTB=${final.ox-dtb}"
];
}; };
uboot-env = let uboot-env = let
@ -155,7 +182,7 @@
#"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions #"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions
#"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions #"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
#"PLATFORM_RISCV_ABI=lp64d" #"PLATFORM_RISCV_ABI=lp64d"
"FW_PAYLOAD_PATH=${final.uboot}/u-boot-nodtb.bin" "FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin"
"FW_FDT_PATH=ox.dtb" "FW_FDT_PATH=ox.dtb"
]; ];
patches = [ ./ox-alveo-platform-plic.patch ]; patches = [ ./ox-alveo-platform-plic.patch ];

229
ox-plic.dts
View File

@ -5,139 +5,138 @@
compatible = "riscv,rv64i"; compatible = "riscv,rv64i";
model = "Barcelona Supercomputing Center - Lagarto Ox"; model = "Barcelona Supercomputing Center - Lagarto Ox";
chosen { chosen {
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash"; bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
}; };
cpus { cpus {
#address-cells = <0x00000001>; #address-cells = <0x00000001>;
#size-cells = <0x00000000>; #size-cells = <0x00000000>;
timebase-frequency = <0x0000c350>; timebase-frequency = <0x0000c350>;
cpu@0 { cpu@0 {
clock-frequency = <0x02FAF080>; clock-frequency = <0x02FAF080>;
device_type = "cpu"; device_type = "cpu";
reg = <0x00000000>; reg = <0x00000000>;
status = "okay"; status = "okay";
compatible = "riscv"; compatible = "riscv";
riscv,isa = "rv64imafd"; riscv,isa = "rv64imafd";
mmu-type = "riscv,sv39"; mmu-type = "riscv,sv39";
tlb-split; tlb-split;
L3: interrupt-controller { L3: interrupt-controller {
#interrupt-cells = <0x00000001>; #interrupt-cells = <0x00000001>;
interrupt-controller; interrupt-controller;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
};
}; };
};
}; };
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x77e00000>; reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
}; };
reserved-memory { reserved-memory {
#address-cells = <0x00000002>; #address-cells = <0x00000002>;
#size-cells = <0x00000002>; #size-cells = <0x00000002>;
ranges; ranges;
eth_pool: dma_pool@60000000 { eth_pool: dma_pool@60000000 {
reg = <0x00000000 0x60000000 0x00000000 0x10000000>; reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
}; };
onic_pool: dma_pool@70000000 { onic_pool: dma_pool@70000000 {
reg = <0x00000000 0x70000000 0x00000000 0x10000000>; reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
}; };
}; };
eth0_clk: eth0_clk { eth0_clk: eth0_clk {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0x00000000>; #clock-cells = <0x00000000>;
clock-frequency = <0x09502f90>; clock-frequency = <0x09502f90>;
}; };
pmem@1bff00000 { pmem@1bff00000 {
volatile; volatile;
compatible = "pmem-region"; compatible = "pmem-region";
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>; reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
}; };
pmem2@1b7f00000 { pmem2@1b7f00000 {
#address-cells = <0x00000002>; #address-cells = <0x00000002>;
#size-cells = <0x00000002>; #size-cells = <0x00000002>;
volatile; volatile;
compatible = "pmem-region"; compatible = "pmem-region";
reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>; reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
}; };
pmem3@f7e00000 { pmem3@f7e00000 {
volatile; volatile;
compatible = "pmem-region"; compatible = "pmem-region";
reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>; reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
}; };
soc { soc {
#address-cells = <0x00000002>; #address-cells = <0x00000002>;
#size-cells = <0x00000002>; #size-cells = <0x00000002>;
compatible = "BSC,Lagarto-bare-soc", "simple-bus"; compatible = "BSC,Lagarto-ox-soc", "simple-bus";
ranges; ranges;
serial@40001000 { serial@40001000 {
compatible = "ns16750"; compatible = "ns16750";
reg = <0x00000000 0x40001000 0x00000000 0x00001000>; reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
interrupts = <0x00000000>; interrupts = <0x00000000>;
port-number = <0x00000000>; port-number = <0x00000000>;
reg-shift = <0x00000002>; reg-shift = <0x00000002>;
clock-frequency = <0x02FAF080>; clock-frequency = <0x02FAF080>;
current-speed = <0x0001c200>; current-speed = <0x0001c200>;
status = "okay"; status = "okay";
};
ethernet0 {
xlnx,rxmem = <0x000005f2>;
carv,mtu = <0x000005dc>;
carv,no-mac;
device_type = "network";
local-mac-address = [02 05 00 01 00 05];
axistream-connected = <0x000000fe>;
compatible = "xlnx,xxv-ethernet-1.0-carv";
memory-region = <&eth_pool>;
};
dma@40400000 {
xlnx,include-dre;
phandle = <0x000000fe>;
#dma-cells = <0x00000001>;
compatible = "xlnx,axi-dma-1.00.a";
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&PLIC0>;
interrupts = <0x00000002 0x00000003>;
xlnx,addrwidth = <0x00000028>;
xlnx,include-sg;
xlnx,sg-length-width = <0x00000017>;
dma-channel@40400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x00000000>;
interrupts = <0x00000002>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
}; };
ethernet0 { dma-channel@40400030 {
xlnx,rxmem = <0x000005f2>; compatible = "xlnx,axi-dma-s2mm-channel";
carv,mtu = <0x000005dc>; dma-channels = <0x00000001>;
carv,no-mac; interrupts = <0x00000003>;
device_type = "network"; xlnx,datawidth = <0x00000040>;
local-mac-address = [02 05 00 01 00 05]; xlnx,device-id = <0x00000000>;
axistream-connected = <0x000000fe>; xlnx,include-dre;
compatible = "xlnx,xxv-ethernet-1.0-carv";
memory-region = <&eth_pool>;
};
dma@40400000 {
xlnx,include-dre;
phandle = <0x000000fe>;
#dma-cells = <0x00000001>;
compatible = "xlnx,axi-dma-1.00.a";
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&PLIC0>;
interrupts = <0x00000002 0x00000003>;
xlnx,addrwidth = <0x00000028>;
xlnx,include-sg;
xlnx,sg-length-width = <0x00000017>;
dma-channel@40400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x00000000>;
interrupts = <0x00000002>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
dma-channel@40400030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000003>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
};
clint@40002000 {
reg-names = "control";
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
compatible = "riscv,clint0";
#interrupt-cells = <0x00000001>;
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
};
PLIC0: plic@40800000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 3 &L3 7>;
reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
riscv,ndev = <0x00000003>;
riscv,max-priority = <0x00000007>;
}; };
};
clint@40002000 {
reg-names = "control";
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
compatible = "riscv,clint0";
#interrupt-cells = <0x00000001>;
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
};
PLIC0: plic@40800000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 3 &L3 7>;
reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
riscv,ndev = <0x00000003>;
riscv,max-priority = <0x00000007>;
};
}; };
}; };

2
ox.dts
View File

@ -35,7 +35,7 @@
uart0: serial@40001000 { uart0: serial@40001000 {
compatible = "ns16750"; compatible = "ns16750";
//reg = <0x40001000 0x1000>; //reg = <0x40001000 0x1000>;
reg = <0x00000000 0x40001000 0x00000000 0x00000100>; reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
interrupts = <0>; interrupts = <0>;
port-number = <0>; port-number = <0>;
reg-shift = <2>; reg-shift = <2>;

83
u-boot-debug.patch Normal file
View File

@ -0,0 +1,83 @@
diff --git a/common/board_f.c b/common/board_f.c
index 1688e27071..216839febb 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -978,6 +978,8 @@ static const init_fnc_t init_sequence_f[] = {
void board_init_f(ulong boot_flags)
{
+ puts("board_init_f() called\n");
+
gd->flags = boot_flags;
gd->have_console = 0;
@@ -990,6 +992,7 @@ void board_init_f(ulong boot_flags)
/* NOTREACHED - jump_to_copy() does not return */
hang();
#endif
+ puts("board_init_f() ends ok\n");
}
#if defined(CONFIG_X86) || defined(CONFIG_ARC)
diff --git a/common/board_r.c b/common/board_r.c
index d798c00a80..cb8119a603 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -786,6 +786,8 @@ static init_fnc_t init_sequence_r[] = {
void board_init_r(gd_t *new_gd, ulong dest_addr)
{
+ puts("board_init_r called\n");
+
/*
* The pre-relocation drivers may be using memory that has now gone
* away. Mark serial as unavailable - this will fall back to the debug
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index d6484d7f4b..64a507248d 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -92,10 +92,13 @@ static int riscv_cpu_get_count(const struct udevice *dev)
static int riscv_cpu_bind(struct udevice *dev)
{
+ puts("riscv_cpu_bind called()\n");
+
struct cpu_plat *plat = dev_get_parent_plat(dev);
struct driver *drv;
int ret;
+ puts("looking for timebase-frequency\n");
/* save the hart id */
plat->cpu_id = dev_read_addr(dev);
/* first examine the property in current cpu node */
@@ -105,6 +108,8 @@ static int riscv_cpu_bind(struct udevice *dev)
dev_read_u32(dev->parent, "timebase-frequency",
&plat->timebase_freq);
+ printf("timebase-frequency=%lu\n", (unsigned long) plat->timebase_freq);
+
/*
* Bind riscv-timer driver on boot hart.
*
@@ -125,6 +130,8 @@ static int riscv_cpu_bind(struct udevice *dev)
device_bind_with_driver_data(dev, drv, "riscv_timer",
plat->timebase_freq, ofnode_null(),
NULL);
+ } else {
+ printf("ignoring cpu_id=%d\n", plat->cpu_id);
}
return 0;
diff --git a/lib/hang.c b/lib/hang.c
index 2735774f9a..84eff21ffc 100644
--- a/lib/hang.c
+++ b/lib/hang.c
@@ -22,6 +22,8 @@
*/
void hang(void)
{
+ puts("oh no, we are in hang()\n");
+
#if !defined(CONFIG_SPL_BUILD) || \
(CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) && \
CONFIG_IS_ENABLED(SERIAL))

278
xavi-good-ftd.dts Normal file
View File

@ -0,0 +1,278 @@
LOx$
OpenSBI v1.2
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : Sargantana (for Xilinx Alveo FPGA)
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : ---
Platform Timer Device : generic_timer @ 25000000Hz
Platform Console Device : alveo_uart
Platform HSM Device : ---
Platform PMU Device : ---
Platform Reboot Device : ---
Platform Shutdown Device : ---
Firmware Base : 0x80000000
Firmware Size : 148 KB
Runtime SBI Version : 1.0
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x0000000080010000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART Priv Version : v1.10
Boot HART Base ISA : rv64imafdc
Boot HART ISA Extensions : time
Boot HART PMP Count : 0
Boot HART PMP Granularity : 0
Boot HART PMP Address Bits: 0
Boot HART MHPM Count : 29
Boot HART MIDELEG : 0x0000000000000222
Boot HART MEDELEG : 0x000000000000b109
<debug_uart>
Core: 9 devices, 8 uclasses, devicetree: separate
MMC:
Loading Environment from <NULL>... OK
In: serial@40001000
Out: serial@40001000
Err: serial@40001000
Model: Barcelona Supercomputing Center - Lagarto Ox
Hit any key to stop autoboot: 0
LOx$ fdt
fdt - flattened device tree utility commands
Usage:
fdt addr [-c] [-q] <addr> [<size>] - Set the [control] fdt location to <addr>
fdt apply <addr> - Apply overlay to the DT
fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active
fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed
fdt print <path> [<prop>] - Recursive print starting at <path>
fdt list <path> [<prop>] - Print one level starting at <path>
fdt get value <var> <path> <prop> [<index>] - Get <property> and store in <var>
In case of stringlist property, use optional <index>
to select string within the stringlist. Default is 0.
fdt get name <var> <path> <index> - Get name of node <index> and store in <var>
fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var>
fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var>
fdt set <path> <prop> [<val>] - Set <property> [to <val>]
fdt mknode <path> <node> - Create a new node after <path>
fdt rm <path> [<prop>] - Delete the node or <property>
fdt header [get <var> <member>] - Display header info
get - get header member <member> and store it in <var>
fdt bootcpu <id> - Set boot cpuid
fdt memory <addr> <size> - Add/Update memory node
fdt rsvmem print - Show current mem reserves
fdt rsvmem add <addr> <size> - Add a mem reserve
fdt rsvmem delete <index> - Delete a mem reserves
fdt chosen [<start> <size>] - Add/update the /chosen branch in the tree
<start>/<size> - initrd start addr/size
NOTE: Dereference aliases by omitting the leading '/', e.g. fdt print ethernet0.
LOx$ fdt print
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
LOx$ fdt list
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
LOx$ printenv
arch=riscv
baudrate=115200
board=riscv64
board_name=riscv64
bootcmd=fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; blkmap create pmem2; blkmap map pmem2 0 0x40000 mem 0x1b7f00000; blkmap info; ls blkmap 0; load blkmap 0 ${kernel_addr_r} Image; setenv bootargs ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash; booti ${kernel_addr_r} - ${fdt_addr_r};
bootdelay=10
cpu=generic
fdt_addr_r=0x86000000
fdtcontroladdr=e7d87e60
image=boot/Image
kernel_addr_r=0x80200000
loadaddr=0x87000000
mmcdev=0
mmcpart=1
stderr=serial@40001000
stdin=serial@40001000
stdout=serial@40001000
vendor=openpiton
Environment size: 640/126972 bytes
LOx$ fdt addr ${fdt_addr_r}
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
LOx$ fdt addr ${fdtcontroladdr}
Working FDT set to e7d87e60
LOx$ fdt print
/ {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "riscv,rv64i";
model = "Barcelona Supercomputing Center - Lagarto Ox";
chosen {
bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
};
cpus {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
timebase-frequency = <0x0000c350>;
cpu@0 {
clock-frequency = <0x02faf080>;
device_type = "cpu";
reg = <0x00000000>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafd";
mmu-type = "riscv,sv39";
tlb-split;
phandle = <0x00000004>;
interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x00000005>;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
};
reserved-memory {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
dma_pool@60000000 {
reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool";
phandle = <0x00000001>;
};
dma_pool@70000000 {
reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool";
phandle = <0x00000006>;
};
};
eth0_clk {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x09502f90>;
phandle = <0x00000002>;
};
pmem@1bff00000 {
volatile;
compatible = "pmem-region";
reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
};
pmem2@1b7f00000 {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
volatile;
compatible = "pmem-region";
reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
};
pmem3@f7e00000 {
volatile;
compatible = "pmem-region";
reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
};
soc {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "BSC,Lagarto-bare-soc", "simple-bus";
ranges;
serial@40001000 {
compatible = "ns16750";
reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
interrupts = <0x00000000>;
port-number = <0x00000000>;
reg-shift = <0x00000002>;
clock-frequency = <0x017d7840>;
current-speed = <0x0001c200>;
status = "okay";
phandle = <0x00000007>;
};
ethernet0 {
xlnx,rxmem = <0x000005f2>;
carv,mtu = <0x000005dc>;
carv,no-mac;
device_type = "network";
local-mac-address = [02 05 00 01 00 05];
axistream-connected = <0x000000fe>;
compatible = "xlnx,xxv-ethernet-1.0-carv";
memory-region = <0x00000001>;
};
dma@40020000 {
xlnx,include-dre;
phandle = <0x000000fe>;
#dma-cells = <0x00000001>;
compatible = "xlnx,axi-dma-1.00.a";
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <0x00000002 0x00000002 0x00000002 0x00000002>;
reg = <0x00000000 0x40200000 0x00000000 0x00400000>;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <0x00000003>;
interrupts = <0x00000002 0x00000003>;
xlnx,addrwidth = <0x00000028>;
xlnx,include-sg;
xlnx,sg-length-width = <0x00000017>;
dma-channel@40020000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000002>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
dma-channel@40020030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000003>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
};
clint@40002000 {
reg-names = "control";
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
compatible = "riscv,clint0";
#interrupt-cells = <0x00000001>;
reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
};
plic@fff1100000 {
#address-cells = <0x00000000>;
compatible = "riscv,plic0";
#interrupt-cells = <0x00000001>;
reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
riscv,ndev = <0x00000003>;
riscv,max-priority = <0x00000007>;
interrupt-controller;
phandle = <0x00000003>;
};
};
__symbols__ {
CPU0 = "/cpus/cpu@0";
CPU0_intc = "/cpus/cpu@0/interrupt-controller";
eth_pool = "/reserved-memory/dma_pool@60000000";
meep_pool = "/reserved-memory/dma_pool@70000000";
eth0_clk = "/eth0_clk";
uart0 = "/soc/serial@40001000";
dma_eth = "/soc/dma@40020000";
PLIC0 = "/soc/plic@fff1100000";
};
};
LOx$