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Claim aux timer interrupt

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This commit is contained in:
Rodrigo Arias Mallo 2024-08-21 11:29:12 +02:00
parent ea081176f7
commit 706d858347
1 changed files with 17 additions and 21 deletions
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38
opensbi-test-plic.patch
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@ -1,5 +1,5 @@
diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c
index 0ae604a..31d8082 100644 index 0ae604a..177fb6b 100644
--- a/lib/sbi/sbi_irqchip.c --- a/lib/sbi/sbi_irqchip.c
+++ b/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c
@@ -9,6 +9,9 @@ @@ -9,6 +9,9 @@
@ -25,7 +25,7 @@ index 0ae604a..31d8082 100644
return 0; return 0;
} }
@@ -47,8 +52,162 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch) @@ -47,8 +52,158 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch)
{ {
const struct sbi_platform *plat = sbi_platform_ptr(scratch); const struct sbi_platform *plat = sbi_platform_ptr(scratch);
@ -147,22 +147,29 @@ index 0ae604a..31d8082 100644
+ volatile unsigned *plic_priority = (unsigned *)(PLIC_BASE + PLIC_PRIORITY_OFFSET + PLIC_TIMER_PORT * 4); + volatile unsigned *plic_priority = (unsigned *)(PLIC_BASE + PLIC_PRIORITY_OFFSET + PLIC_TIMER_PORT * 4);
+ volatile unsigned *plic_enable = (unsigned *)(PLIC_BASE + PLIC_ENABLE_OFFSET); + volatile unsigned *plic_enable = (unsigned *)(PLIC_BASE + PLIC_ENABLE_OFFSET);
+ volatile unsigned *plic_threshold = (unsigned *)(PLIC_BASE + PLIC_THRESHOLD_OFFSET); + volatile unsigned *plic_threshold = (unsigned *)(PLIC_BASE + PLIC_THRESHOLD_OFFSET);
+ volatile unsigned *plic_claim = (unsigned *)(PLIC_BASE + PLIC_CLAIM_OFFSET);
+ volatile unsigned *plic_pending = (unsigned *)(PLIC_BASE + PLIC_PENDING_OFFSET);
+ +
+ sbi_printf("Enabling timer in PLIC\n");
+ *plic_priority = PLIC_TIMER_PORT; + *plic_priority = PLIC_TIMER_PORT;
+ *plic_threshold = PLIC_TIMER_PORT - 1; + *plic_threshold = PLIC_TIMER_PORT - 1;
+ *plic_enable |= (1 << PLIC_TIMER_PORT); + *plic_enable |= (1 << PLIC_TIMER_PORT);
+ +
+ sbi_printf("Timer enabled in PLIC\n"); + /* Clear interrupt */
+ sbi_printf("Pending: %d\n", *plic_pending);
+ unsigned claim = *plic_claim;
+ sbi_printf("Claim: %d\n", claim);
+ *plic_claim = claim;
+ sbi_printf("Pending: %d\n", *plic_pending);
+ +
+ /* + sbi_printf("Clearing MIP\n");
+ * Clear mip CSR before proceeding with init to avoid any spurious
+ * external interrupts in S-mode.
+ */
+ csr_write(CSR_MIP, 0); + csr_write(CSR_MIP, 0);
+ +
+ /* Enable external timer interrupts */ + /* Enable external timer interrupts */
+ csr_set(CSR_MIE, MIE_MEIE); /* Needed? */ + //sbi_printf("Enabling MEIE in MIE register\n");
+ csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */ + //csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
+ //sbi_printf("Enabling MIE in MSTATUS register\n");
+ //csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
+ +
+ /* Enable timer interrupt */ + /* Enable timer interrupt */
+ *mtimecmp = *mtime + 10000; + *mtimecmp = *mtime + 10000;
@ -172,21 +179,10 @@ index 0ae604a..31d8082 100644
+ +
+ dumpregs(); + dumpregs();
+ +
+ // Switch to supervisor mode and execute supervisor_mode_code
+ switch_to_supervisor_mode(&supervisor_mode_code); + switch_to_supervisor_mode(&supervisor_mode_code);
+ +
+ /* Never reached */ + /* Never reached */
+ + while (1);
+ int count = 0;
+ // Main loop
+ while (1) {
+ if (count == 10000) {
+ sbi_printf("Still in machine mode\n");
+ count = 0;
+ }
+ count++;
+ // Main application code
+ }
+} +}
+ +
+ +