From 706d858347b542ad2de161210edd0836a02701a3 Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodarima@gmail.com>
Date: Wed, 21 Aug 2024 11:29:12 +0200
Subject: [PATCH] Claim aux timer interrupt

---
 opensbi-test-plic.patch | 38 +++++++++++++++++---------------------
 1 file changed, 17 insertions(+), 21 deletions(-)

diff --git a/opensbi-test-plic.patch b/opensbi-test-plic.patch
index 4697f00..c9f8837 100644
--- a/opensbi-test-plic.patch
+++ b/opensbi-test-plic.patch
@@ -1,5 +1,5 @@
 diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c
-index 0ae604a..31d8082 100644
+index 0ae604a..177fb6b 100644
 --- a/lib/sbi/sbi_irqchip.c
 +++ b/lib/sbi/sbi_irqchip.c
 @@ -9,6 +9,9 @@
@@ -25,7 +25,7 @@ index 0ae604a..31d8082 100644
  
  	return 0;
  }
-@@ -47,8 +52,162 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch)
+@@ -47,8 +52,158 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch)
  {
  	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
  
@@ -147,22 +147,29 @@ index 0ae604a..31d8082 100644
 +	volatile unsigned *plic_priority  = (unsigned *)(PLIC_BASE + PLIC_PRIORITY_OFFSET + PLIC_TIMER_PORT * 4);
 +	volatile unsigned *plic_enable    = (unsigned *)(PLIC_BASE + PLIC_ENABLE_OFFSET);
 +	volatile unsigned *plic_threshold = (unsigned *)(PLIC_BASE + PLIC_THRESHOLD_OFFSET);
++	volatile unsigned *plic_claim     = (unsigned *)(PLIC_BASE + PLIC_CLAIM_OFFSET);
++	volatile unsigned *plic_pending   = (unsigned *)(PLIC_BASE + PLIC_PENDING_OFFSET);
 +
++	sbi_printf("Enabling timer in PLIC\n");
 +	*plic_priority = PLIC_TIMER_PORT;
 +	*plic_threshold = PLIC_TIMER_PORT - 1;
 +	*plic_enable |= (1 << PLIC_TIMER_PORT);
 +
-+	sbi_printf("Timer enabled in PLIC\n");
++	/* Clear interrupt */
++	sbi_printf("Pending: %d\n", *plic_pending);
++	unsigned claim = *plic_claim;
++	sbi_printf("Claim: %d\n", claim);
++	*plic_claim = claim;
++	sbi_printf("Pending: %d\n", *plic_pending);
 +
-+	/*
-+	 * Clear mip CSR before proceeding with init to avoid any spurious
-+	 * external interrupts in S-mode.
-+	 */
++	sbi_printf("Clearing MIP\n");
 +	csr_write(CSR_MIP, 0);
 +
 +	/* Enable external timer interrupts */
-+	csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
-+	csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
++	//sbi_printf("Enabling MEIE in MIE register\n");
++	//csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
++	//sbi_printf("Enabling MIE in MSTATUS register\n");
++	//csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
 +
 +	/* Enable timer interrupt */
 +	*mtimecmp = *mtime + 10000;
@@ -172,21 +179,10 @@ index 0ae604a..31d8082 100644
 +
 +	dumpregs();
 +
-+	// Switch to supervisor mode and execute supervisor_mode_code
 +	switch_to_supervisor_mode(&supervisor_mode_code);
 +
 +	/* Never reached */
-+
-+	int count = 0;
-+	// Main loop
-+	while (1) {
-+		if (count == 10000) {
-+			sbi_printf("Still in machine mode\n");
-+			count = 0;
-+		}
-+		count++;
-+		// Main application code
-+	}
++	while (1);
 +}
 +
 +