rarias/nixos-riscv
1
0
Fork 0
Code Issues Pull Requests 1 Actions Packages Projects Releases Wiki Activity

Revert "Try to use openpiton based OpenSBI config"

Browse Source 
This reverts commit 931244a355.
This commit is contained in:
Rodrigo Arias 2024-07-08 10:03:48 +02:00
parent 1b4ab09c16
commit 6721e1e22c
2 changed files with 9 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lagarto-ox.nix
View File

@ -255,17 +255,16 @@
'';
opensbi = prev.opensbi.overrideAttrs (old: rec {
#version = "1.4";
#src = prev.fetchFromGitHub {
# owner = "riscv-software-src";
# repo = "opensbi";
# rev = "v${version}";
# hash = "sha256-T8ZeAzjM9aeTXitjE7s+m+jjGGtDo2jK1qO5EuKiVLU=";
#};
version = "1.4";
src = prev.fetchFromGitHub {
owner = "riscv-software-src";
repo = "opensbi";
rev = "v${version}";
hash = "sha256-T8ZeAzjM9aeTXitjE7s+m+jjGGtDo2jK1qO5EuKiVLU=";
};
#NIX_DEBUG=5;
makeFlags = [
"PLATFORM=fpga/openpiton"
#"PLATFORM=fpga/ox_alveo"
"PLATFORM=fpga/ox_alveo"
#"CONFIG_SBI_ECALL_RFENCE=n"
#"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions
#"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions
@ -273,7 +272,7 @@
"FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin"
"FW_FDT_PATH=${final.ox-dtb}"
];
patches = [ ./opensbi-lagarto-ox.patch ];
patches = [ ./ox-alveo-platform-plic.patch ];
});
# opensbi = prev.opensbi.overrideAttrs (old: {
# #NIX_DEBUG=5;

26
opensbi-lagarto-ox.patch
View File

@ -1,26 +0,0 @@
diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c
index 2317a89..4a83ca9 100644
--- a/platform/fpga/openpiton/platform.c
+++ b/platform/fpga/openpiton/platform.c
@@ -17,17 +17,17 @@
#include <sbi_utils/serial/uart8250.h>
#include <sbi_utils/timer/aclint_mtimer.h>
-#define OPENPITON_DEFAULT_UART_ADDR 0xfff0c2c000
-#define OPENPITON_DEFAULT_UART_FREQ 60000000
+#define OPENPITON_DEFAULT_UART_ADDR 0x40001000
+#define OPENPITON_DEFAULT_UART_FREQ 50000000
#define OPENPITON_DEFAULT_UART_BAUDRATE 115200
#define OPENPITON_DEFAULT_UART_REG_SHIFT 0
#define OPENPITON_DEFAULT_UART_REG_WIDTH 1
-#define OPENPITON_DEFAULT_UART_REG_OFFSET 0
+#define OPENPITON_DEFAULT_UART_REG_OFFSET 0x1000
#define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000
#define OPENPITON_DEFAULT_PLIC_SIZE (0x200000 + \
(OPENPITON_DEFAULT_HART_COUNT * 0x1000))
#define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2
-#define OPENPITON_DEFAULT_HART_COUNT 3
+#define OPENPITON_DEFAULT_HART_COUNT 1
#define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000
#define OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ 1000000
#define OPENPITON_DEFAULT_ACLINT_MSWI_ADDR \