From 6721e1e22ca0aefad64a47f1882f2ee3cbd6bab7 Mon Sep 17 00:00:00 2001 From: Rodrigo Arias Mallo Date: Mon, 8 Jul 2024 10:03:48 +0200 Subject: [PATCH] Revert "Try to use openpiton based OpenSBI config" This reverts commit 931244a355d82c371af3f2419df376d1f6da2ec3. --- lagarto-ox.nix | 19 +++++++++---------- opensbi-lagarto-ox.patch | 26 -------------------------- 2 files changed, 9 insertions(+), 36 deletions(-) delete mode 100644 opensbi-lagarto-ox.patch diff --git a/lagarto-ox.nix b/lagarto-ox.nix index 71f0e49..37543d2 100644 --- a/lagarto-ox.nix +++ b/lagarto-ox.nix @@ -255,17 +255,16 @@ ''; opensbi = prev.opensbi.overrideAttrs (old: rec { - #version = "1.4"; - #src = prev.fetchFromGitHub { - # owner = "riscv-software-src"; - # repo = "opensbi"; - # rev = "v${version}"; - # hash = "sha256-T8ZeAzjM9aeTXitjE7s+m+jjGGtDo2jK1qO5EuKiVLU="; - #}; + version = "1.4"; + src = prev.fetchFromGitHub { + owner = "riscv-software-src"; + repo = "opensbi"; + rev = "v${version}"; + hash = "sha256-T8ZeAzjM9aeTXitjE7s+m+jjGGtDo2jK1qO5EuKiVLU="; + }; #NIX_DEBUG=5; makeFlags = [ - "PLATFORM=fpga/openpiton" - #"PLATFORM=fpga/ox_alveo" + "PLATFORM=fpga/ox_alveo" #"CONFIG_SBI_ECALL_RFENCE=n" #"PLATFORM_RISCV_ISA=rv64imafd" # No compressed instructions #"PLATFORM_RISCV_ISA=rv64g" # No compressed instructions @@ -273,7 +272,7 @@ "FW_PAYLOAD_PATH=${final.uboot}/u-boot.bin" "FW_FDT_PATH=${final.ox-dtb}" ]; - patches = [ ./opensbi-lagarto-ox.patch ]; + patches = [ ./ox-alveo-platform-plic.patch ]; }); # opensbi = prev.opensbi.overrideAttrs (old: { # #NIX_DEBUG=5; diff --git a/opensbi-lagarto-ox.patch b/opensbi-lagarto-ox.patch deleted file mode 100644 index d3dfce8..0000000 --- a/opensbi-lagarto-ox.patch +++ /dev/null @@ -1,26 +0,0 @@ -diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c -index 2317a89..4a83ca9 100644 ---- a/platform/fpga/openpiton/platform.c -+++ b/platform/fpga/openpiton/platform.c -@@ -17,17 +17,17 @@ - #include - #include - --#define OPENPITON_DEFAULT_UART_ADDR 0xfff0c2c000 --#define OPENPITON_DEFAULT_UART_FREQ 60000000 -+#define OPENPITON_DEFAULT_UART_ADDR 0x40001000 -+#define OPENPITON_DEFAULT_UART_FREQ 50000000 - #define OPENPITON_DEFAULT_UART_BAUDRATE 115200 - #define OPENPITON_DEFAULT_UART_REG_SHIFT 0 - #define OPENPITON_DEFAULT_UART_REG_WIDTH 1 --#define OPENPITON_DEFAULT_UART_REG_OFFSET 0 -+#define OPENPITON_DEFAULT_UART_REG_OFFSET 0x1000 - #define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000 - #define OPENPITON_DEFAULT_PLIC_SIZE (0x200000 + \ - (OPENPITON_DEFAULT_HART_COUNT * 0x1000)) - #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2 --#define OPENPITON_DEFAULT_HART_COUNT 3 -+#define OPENPITON_DEFAULT_HART_COUNT 1 - #define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000 - #define OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ 1000000 - #define OPENPITON_DEFAULT_ACLINT_MSWI_ADDR \