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Clear MIP before enabling timer

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This commit is contained in:
Rodrigo Arias Mallo 2024-08-21 10:09:06 +02:00
parent 90df8a3ccb
commit 64cc2a982f
1 changed files with 8 additions and 2 deletions
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10
opensbi-test-plic.patch
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@ -1,5 +1,5 @@
diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c
index 0ae604a..3708c3a 100644 index 0ae604a..0314715 100644
--- a/lib/sbi/sbi_irqchip.c --- a/lib/sbi/sbi_irqchip.c
+++ b/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c
@@ -9,6 +9,9 @@ @@ -9,6 +9,9 @@
@ -25,7 +25,7 @@ index 0ae604a..3708c3a 100644
return 0; return 0;
} }
@@ -47,8 +52,156 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch) @@ -47,8 +52,162 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch)
{ {
const struct sbi_platform *plat = sbi_platform_ptr(scratch); const struct sbi_platform *plat = sbi_platform_ptr(scratch);
@ -158,6 +158,12 @@ index 0ae604a..3708c3a 100644
+// csr_set(CSR_MIE, MIE_MEIE); /* Needed? */ +// csr_set(CSR_MIE, MIE_MEIE); /* Needed? */
+// csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */ +// csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */
+ +
+ /*
+ * Clear mip CSR before proceeding with init to avoid any spurious
+ * external interrupts in S-mode.
+ */
+ csr_write(CSR_MIP, 0);
+
+ /* Enable timer interrupt */ + /* Enable timer interrupt */
+ *mtimecmp = *mtime + 10000; + *mtimecmp = *mtime + 10000;
+ +