From 64cc2a982f80fced695e6c2b989c4c5364b2853b Mon Sep 17 00:00:00 2001 From: Rodrigo Arias Mallo Date: Wed, 21 Aug 2024 10:09:06 +0200 Subject: [PATCH] Clear MIP before enabling timer --- opensbi-test-plic.patch | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/opensbi-test-plic.patch b/opensbi-test-plic.patch index 6a900dd..07dbc25 100644 --- a/opensbi-test-plic.patch +++ b/opensbi-test-plic.patch @@ -1,5 +1,5 @@ diff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c -index 0ae604a..3708c3a 100644 +index 0ae604a..0314715 100644 --- a/lib/sbi/sbi_irqchip.c +++ b/lib/sbi/sbi_irqchip.c @@ -9,6 +9,9 @@ @@ -25,7 +25,7 @@ index 0ae604a..3708c3a 100644 return 0; } -@@ -47,8 +52,156 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch) +@@ -47,8 +52,162 @@ void sbi_irqchip_exit(struct sbi_scratch *scratch) { const struct sbi_platform *plat = sbi_platform_ptr(scratch); @@ -158,6 +158,12 @@ index 0ae604a..3708c3a 100644 +// csr_set(CSR_MIE, MIE_MEIE); /* Needed? */ +// csr_set(CSR_MSTATUS, MSTATUS_MIE); /* Needed? */ + ++ /* ++ * Clear mip CSR before proceeding with init to avoid any spurious ++ * external interrupts in S-mode. ++ */ ++ csr_write(CSR_MIP, 0); ++ + /* Enable timer interrupt */ + *mtimecmp = *mtime + 10000; +