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Add lagarto hun DTS file

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This commit is contained in:
Rodrigo Arias 2024-03-04 14:46:26 +01:00
parent 7c58298de6
commit 409d2caecc
1 changed files with 185 additions and 0 deletions
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185
fpga/lagarto_hun.dts Normal file
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@ -0,0 +1,185 @@
=> fdt print
/ {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "BSC,Lagarto-bare-dev";
model = "BSC,Lagarto-bare";
chosen {
};
cpus {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
timebase-frequency = <0x0005f5e1>;
cpu@0 {
clock-frequency = <0x02faf080>;
device_type = "cpu";
reg = <0x00000000>;
status = "okay";
compatible = "BSC, Lagarto", "riscv";
riscv,isa = "rv64imafdcv";
mmu-type = "riscv,sv39";
tlb-split;
interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x00000004>;
};
};
cpu@1 {
clock-frequency = <0x02faf080>;
device_type = "cpu";
reg = <0x00000001>;
status = "okay";
compatible = "BSC, Lagarto", "riscv";
riscv,isa = "rv64imafdcv";
mmu-type = "riscv,sv39";
tlb-split;
interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x00000005>;
};
};
cpu@2 {
clock-frequency = <0x02faf080>;
device_type = "cpu";
reg = <0x00000002>;
status = "okay";
compatible = "BSC, Lagarto", "riscv";
riscv,isa = "rv64imafdcv";
mmu-type = "riscv,sv39";
tlb-split;
interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x00000006>;
};
};
cpu@3 {
clock-frequency = <0x02faf080>;
device_type = "cpu";
reg = <0x00000003>;
status = "okay";
compatible = "BSC, Lagarto", "riscv";
riscv,isa = "rv64imafdcv";
mmu-type = "riscv,sv39";
tlb-split;
interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x00000007>;
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000001 0x80000000>;
};
reserved-memory {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
mmode_resv1@80000000 {
reg = <0x00000000 0x80000000 0x00000000 0x00040000>;
no-map;
};
mmode_resv0@80040000 {
reg = <0x00000000 0x80040000 0x00000000 0x00020000>;
no-map;
};
eth_pool_node {
reg = <0x00000080 0x40000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool";
phandle = <0x00000002>;
};
onic_pool_node {
reg = <0x00000080 0x70000000 0x00000000 0x10000000>;
compatible = "shared-dma-pool";
};
};
eth0_clk {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x09502f90>;
phandle = <0x00000003>;
};
soc {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
compatible = "BSC,Lagarto-bare-soc", "simple-bus";
ranges;
uart@fff0c2c000 {
compatible = "ns16550";
reg = <0x000000ff 0xf0c2c000 0x00000000 0x000d4000>;
clock-frequency = <0x02faf080>;
current-speed = <0x0001c200>;
device_type = "serial";
interrupt-parent = <0x00000001>;
interrupts = <0x00000001>;
reg-offset = <0x00001000>;
reg-shift = <0x00000000>;
};
ethernet0 {
xlnx,rxmem = <0x000005f2>;
carv,mtu = <0x000005dc>;
carv,no-mac;
device_type = "network";
local-mac-address = [00 0a 35 23 07 84];
axistream-connected = <0x000000fe>;
compatible = "xlnx,xxv-ethernet-1.0-carv";
memory-region = <0x00000002>;
};
dma@fff0800000 {
xlnx,include-dre;
phandle = <0x000000fe>;
#dma-cells = <0x00000001>;
compatible = "xlnx,axi-dma-1.00.a";
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <0x00000003 0x00000003 0x00000003 0x00000003>;
reg = <0x000000ff 0xf0800000 0x00000000 0x00400000>;
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <0x00000001>;
interrupts = <0x00000002 0x00000003>;
xlnx,addrwidth = <0x00000028>;
xlnx,include-sg;
xlnx,sg-length-width = <0x00000017>;
dma-channel@fff0800000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000002>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
dma-channel@fff0800030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x00000001>;
interrupts = <0x00000003>;
xlnx,datawidth = <0x00000040>;
xlnx,device-id = <0x00000000>;
xlnx,include-dre;
};
};
clint@fff1020000 {
compatible = "riscv,clint0";
interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
reg = <0x000000ff 0xf1020000 0x00000000 0x000c0000>;
reg-names = "control";
};
plic@fff1100000 {
#address-cells = <0x00000000>;
#interrupt-cells = <0x00000001>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <0x00000004 0xffffffff 0x00000004 0x00000009 0x00000005 0xffffffff 0x00000005 0x00000009 0x00000006 0xffffffff 0x00000006 0x00000009 0x00000007 0xffffffff 0x00000007 0x00000009>;
reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
riscv,max-priority = <0x00000007>;
riscv,ndev = <0x00000003>;
phandle = <0x00000001>;
};
};
};