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Revert UART speed to 50MHz following vivado log

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> UART Name g_UART IntfLabel m_axi_uart SyncClk {Label CLK0 Freq 50000000
> Name clk_i} BaseAddr 0x0 Number 2 AxiAddrWidth 0 AxiDataWidth 0 AxiIdWidth
> 0 AxiUserWidth 0 Mode normal IRQ uart_irq
This commit is contained in:
Rodrigo Arias 2024-07-04 17:57:26 +02:00
parent 7eeb16ecfb
commit 05898c5f85
2 changed files with 3 additions and 3 deletions
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2
ox-alveo-platform-plic.patch
View File

@ -55,7 +55,7 @@ index 0000000..a359b34
+ +
+#define OX_ALVEO_UART_BASE_ADDR 0x40000000 +#define OX_ALVEO_UART_BASE_ADDR 0x40000000
+#define OX_ALVEO_UART_OFFSET 0x1000 +#define OX_ALVEO_UART_OFFSET 0x1000
+#define OX_ALVEO_UART_INPUT_FREQ 25000000 +#define OX_ALVEO_UART_INPUT_FREQ 50000000
+#define OX_ALVEO_UART_BAUDRATE 115200 +#define OX_ALVEO_UART_BAUDRATE 115200
+#define OX_ALVEO_PLIC_ADDR 0x40800000 +#define OX_ALVEO_PLIC_ADDR 0x40800000
+#define OX_ALVEO_PLIC_NUM_SOURCES 3 +#define OX_ALVEO_PLIC_NUM_SOURCES 3

4
ox-plic.dts
View File

@ -103,7 +103,7 @@
reg-shift = <2>; reg-shift = <2>;
/* No interrupts for this UART, use console=hvc0 */ /* No interrupts for this UART, use console=hvc0 */
/* This clock is the SERIAL_CLK */ /* This clock is the SERIAL_CLK */
clock-frequency = <25000000>; clock-frequency = <50000000>;
current-speed = <115200>; current-speed = <115200>;
status = "okay"; status = "okay";
}; };
@ -114,7 +114,7 @@
interrupts = <1>; /* Output interrupt 1 */ interrupts = <1>; /* Output interrupt 1 */
interrupt-parent = <&PLIC>; interrupt-parent = <&PLIC>;
reg-shift = <2>; reg-shift = <2>;
clock-frequency = <25000000>; clock-frequency = <50000000>;
current-speed = <115200>; current-speed = <115200>;
status = "okay"; status = "okay";
}; };