From 05898c5f853866ffd7c2255969bf56a14e43e361 Mon Sep 17 00:00:00 2001 From: Rodrigo Arias Mallo Date: Thu, 4 Jul 2024 17:57:26 +0200 Subject: [PATCH] Revert UART speed to 50MHz following vivado log > UART Name g_UART IntfLabel m_axi_uart SyncClk {Label CLK0 Freq 50000000 > Name clk_i} BaseAddr 0x0 Number 2 AxiAddrWidth 0 AxiDataWidth 0 AxiIdWidth > 0 AxiUserWidth 0 Mode normal IRQ uart_irq --- ox-alveo-platform-plic.patch | 2 +- ox-plic.dts | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ox-alveo-platform-plic.patch b/ox-alveo-platform-plic.patch index 5f13c3b..cd54047 100644 --- a/ox-alveo-platform-plic.patch +++ b/ox-alveo-platform-plic.patch @@ -55,7 +55,7 @@ index 0000000..a359b34 + +#define OX_ALVEO_UART_BASE_ADDR 0x40000000 +#define OX_ALVEO_UART_OFFSET 0x1000 -+#define OX_ALVEO_UART_INPUT_FREQ 25000000 ++#define OX_ALVEO_UART_INPUT_FREQ 50000000 +#define OX_ALVEO_UART_BAUDRATE 115200 +#define OX_ALVEO_PLIC_ADDR 0x40800000 +#define OX_ALVEO_PLIC_NUM_SOURCES 3 diff --git a/ox-plic.dts b/ox-plic.dts index 139ba51..018c2e8 100644 --- a/ox-plic.dts +++ b/ox-plic.dts @@ -103,7 +103,7 @@ reg-shift = <2>; /* No interrupts for this UART, use console=hvc0 */ /* This clock is the SERIAL_CLK */ - clock-frequency = <25000000>; + clock-frequency = <50000000>; current-speed = <115200>; status = "okay"; }; @@ -114,7 +114,7 @@ interrupts = <1>; /* Output interrupt 1 */ interrupt-parent = <&PLIC>; reg-shift = <2>; - clock-frequency = <25000000>; + clock-frequency = <50000000>; current-speed = <115200>; status = "okay"; };