272 lines
8.0 KiB
Plaintext
272 lines
8.0 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>; /* 64 bits memory addresses */
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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aliases {
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serial0 = &uart_console; // ttyS0
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// serial1 = &uart_testing; // ttyS1
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};
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// chosen {
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// bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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// };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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// The RTC timer is clocked at the CPU frequency / 1525, so
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// around 32786.88 Hz
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timebase-frequency = <32786>;
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CPU0: cpu@0 {
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clock-frequency = <50000000>; /* 50 MHz */
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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// OpenPiton+Ariane Platform
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// L1I Size / Assoc: 16 kB / 4
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// L1D Size / Assoc: 32 kB / 4
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// L15 Size / Assoc: 128 kB / 8
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// L2 Size / Assoc: 256 kB / 4
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// L15/L1D Cacheline size 64
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i-cache-block-size = <64>; // Guess
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i-cache-sets = <4>;
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i-cache-size = <16384>;
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i-tlb-sets = <1>; // Guess
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i-tlb-size = <32>; // Guess
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d-cache-block-size = <64>; // Guess
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d-cache-sets = <4>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>; // Guess
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d-tlb-size = <32>; // Guess
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phandle = <0x00000004>;
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/* Hart-Level Interrupt Controller: Every interrupt is
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* ultimately routed through a hart's HLIC before it
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* interrupts that hart. */
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HLIC0: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller; /* Receives interrupts */
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compatible = "riscv,cpu-intc";
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phandle = <0x5>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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};
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};
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};
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/* Memory layout:
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*
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* [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
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* [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
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* [0x0_8000_0000, 0x0_b000_0000) -> RAM memory (768 MiB)
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* [0x0_b000_0000, 0x0_c000_0000) -> Broken? (256 MiB)
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* [0x0_c000_0000, 0x1_0000_0000) -> Empty (1024 MiB)
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* [0x1_0000_0000, 0x1_c000_0000) -> PMEM (3072 MiB)
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* [0x1_c000_0000, 0x2_8000_0000) -> Empty (3072 MiB)
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*/
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x30000000>;
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};
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reserved-memory {
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#address-cells = <2>; /* Starting address and size */
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#size-cells = <2>; /* 64 bits memory addresses */
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ranges;
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eth_pool: dma_pool@60000000 {
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reg = <0x0 0x60000000 0x0 0x10000000>;
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compatible = "shared-dma-pool";
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};
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onic_pool: dma_pool@70000000 {
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reg = <0x0 0x70000000 0x0 0x10000000>;
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compatible = "shared-dma-pool";
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};
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};
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dma_clk: dma_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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phandle = <0x00000002>;
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};
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pmem@100000000 {
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/* volatile; This property indicates that this region is
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* actually backed by non-persistent memory. This lets the OS
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* know that it may skip the cache flushes required to ensure
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* data is made persistent after a write. */
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volatile;
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compatible = "pmem-region";
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reg = <0x1 0x00000000 0x0 0xc0000000>;
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};
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soc {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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ranges;
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/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
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* consoles */
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/* The serial for the kernel console */
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uart_console: serial@40001000 {
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compatible = "ns16550";
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reg = <0x0 0x40001000 0x0 0x1000>;
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reg-shift = <2>;
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/* No interrupts for this UART, use console=hvc0 */
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/* This clock is the SERIAL_CLK */
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clock-frequency = <50000000>;
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current-speed = <115200>;
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status = "okay";
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};
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/* The serial for interrupt tests */
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uart_testing: serial@40003000 {
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compatible = "ns16550";
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reg = <0x0 0x40003000 0x0 0x1000>;
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reg-shift = <2>;
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/* Output interrupt 1 (the first one) */
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interrupts = <1>;
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interrupt-parent = <&PLIC>;
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clock-frequency = <50000000>;
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current-speed = <115200>;
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status = "okay";
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};
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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carv,mtu = <0x000005dc>;
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carv,no-mac;
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device_type = "network";
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// 02:$node:00:01:00:$fpga -> 02:05:00:01:00:02
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// 10.5.1.$N/16 -> 10.5.1.184/16
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// N = 150 + ($node - 1) * 8 + $fpga
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local-mac-address = [00 00 00 00 00 00];
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axistream-connected = <&axi_dma>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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};
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axi_dma: dma@40400000 {
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xlnx,include-dre;
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#dma-cells = <0x00000001>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <&dma_clk>, <&dma_clk>, <&dma_clk>, <&dma_clk>;
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reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <&PLIC>;
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interrupts = <2 3>;
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xlnx,addrwidth = <0x28>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x17>;
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dma-channel@40400000 {
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0>;
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interrupts = <2>;
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xlnx,datawidth = <0x40>;
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xlnx,device-id = <0x0>;
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xlnx,include-dre;
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};
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dma-channel@40400030 {
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <1>;
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interrupts = <3>;
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xlnx,datawidth = <0x40>;
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xlnx,device-id = <0x0>;
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xlnx,include-dre;
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};
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};
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/* Platform-Level Interrupt Controller: Delivers interrupts to
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* HARTs. */
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PLIC: plic@40800000 {
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compatible = "riscv,plic0";
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interrupt-controller; /* Receives interrupts */
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#address-cells = <0>;
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#interrupt-cells = <1>;
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/* Sends interrupts to HART interrupt controllers */
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/*
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* From: linux-6.6.1/arch/riscv/include/asm/csr.h
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*
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* Interrupt causes (minus the high bit)
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* #define IRQ_S_SOFT 1
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* #define IRQ_VS_SOFT 2
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* #define IRQ_M_SOFT 3
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* #define IRQ_S_TIMER 5
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* #define IRQ_VS_TIMER 6
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* #define IRQ_M_TIMER 7
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* #define IRQ_S_EXT 9
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* #define IRQ_VS_EXT 10
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* #define IRQ_M_EXT 11
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* #define IRQ_S_GEXT 12
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* #define IRQ_PMU_OVF 13
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* #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
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* #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
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*/
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interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
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reg = < 0x0 0x40800000 0x0 0x00400000>;
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riscv,ndev = <4>;
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//riscv,max-priority = <0x7>;
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phandle = <0x3>;
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};
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/* Core Local Interruptor: It directly connects to the timer and
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* inter-processor interrupt lines of various HARTs (or CPUs) so
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* RISC-V per-HART (or per-CPU) local interrupt controller is
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* the parent interrupt controller for CLINT device. The clock
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* frequency of CLINT is specified via "timebase-frequency" DT
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* property of "/cpus" DT node. The "timebase-frequency" DT
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* property is described in
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* Documentation/devicetree/bindings/riscv/cpus.yaml
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*/
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clint: clint@40100000 {
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reg = <0x0 0x40100000 0x0 0x00010000>;
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reg-names = "control";
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interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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compatible = "riscv,clint0";
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};
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// aux_timer: clint@40010000 {
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// reg = <0x0 0x40010000 0x0 0x00010000>;
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// reg-names = "control";
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// interrupts = <4>; /* PLIC input source 4 */
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// interrupt-parent = <&PLIC>;
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// compatible = "riscv,clint0";
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// };
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// clint: clint@40002000 {
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// /* MTIME and MTIMECMP address and size pairs */
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// reg = <0x0 0x40002000 0x0 0x8>, <0x0 0x40002008 0x0 0x8>;
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// interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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// /*<&CPU0 0x3>, <&CPU0 0x7>,*/
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// /*<&onic_pool 0x3>, <&onic_pool 0x7>,*/
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// /*<&SERIAL 0x3>, <&SERIAL 0x7>*/
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//
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// /* Allows using the "generic" platform in OpenSBI. */
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// compatible = "riscv,aclint-mtimer";
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// };
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/* Guesswork: There must be a timer at 0x40170000 as it is
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* initialized in OpenSBI. It seems to drive the console. */
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//SERIAL_CLK: timer@40170000 {
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// clock-frequency = <100000000>;
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// clocks = <&clk_bus_0>;
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// compatible = "xlnx,xps-timer-1.00.a";
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// interrupt-parent = <&axi_intc_1>;
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// interrupts = <2 2>;
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// reg = <0x41c00000 0x10000>;
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// xlnx,count-width = <0x20>;
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// xlnx,one-timer-only = <0x0>;
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//};
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};
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};
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