77 lines
1.8 KiB
C
77 lines
1.8 KiB
C
/* Toggles */
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#define ENABLE_UART0
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#define ENABLE_UART1
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#define ENABLE_ETHERNET
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#define ENABLE_AXIDMA
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#define ENABLE_PLIC
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#define ENABLE_CLINT
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//#define ENABLE_SPI
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#define CPU_FREQ 50000000 /* 50 MHz */
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/* FIXME: The real RTC frequency is around half that, as the divider was wrongly
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* configured. So for now lets use the real frequency:
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* 50e6 / (1525*2) = 16393.44262295082 -> 16393 Hz */
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#define RTC_FREQ 16393
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/* Memory layout:
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*
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* [0x0_4000_0000, 0x0_6000_0000) -> IO (512 MiB)
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* [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
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* [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
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* [0x0_8000_0000, 0x1_8000_0000) -> RAM memory (4 GiB)
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* [0x1_8000_0000, 0x1_c000_0000) -> Unused (1 GiB)
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* [0x1_c000_0000, 0x2_8000_0000) -> PMEM (3 GiB)
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*/
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#define UART0_SPEED 115200
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#define UART0_ADDR 0x40001000
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#define UART0_SIZE 0x00001000
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#define UART1_SPEED UART0_SPEED
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#define UART1_ADDR 0x40003000
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#define UART1_SIZE 0x00001000
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/* UART2 via SPI */
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#define UART2_SPEED UART0_SPEED
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#define UART2_ADDR 0x40005000
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#define UART2_SIZE 0x00001000
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#define SPI_ADDR 0x40007000
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#define SPI_SIZE 0x00001000
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#define AUXTIMER_ADDR 0x40010000
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#define AUXTIMER_SIZE 0x00010000
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#define CLINT_ADDR 0x40100000
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#define CLINT_SIZE 0x00010000
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#define AXIDMA_ADDR 0x40400000
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#define AXIDMA_SIZE 0x00400000
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#define AXIDMA_CH0 0x40400000
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#define AXIDMA_CH1 0x40400030
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#define AXIDMA_FREQ 156250000
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#define PLIC_ADDR 0x40800000
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#define PLIC_SIZE 0x00400000
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#ifdef ENABLE_SPI
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# define PLIC_NDEV 7 /* extra UART2 + 2 x SPI */
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#else
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# define PLIC_NDEV 4
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#endif
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#define ETHPOOL_ADDR 0x60000000
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#define ETHPOOL_SIZE 0x10000000
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#define ONICPOOL_ADDR 0x70000000
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#define ONICPOOL_SIZE 0x10000000
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/* Notice addresses > 32 bits from here */
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#define MEM_ADDR 0x080000000
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#define MEM_SIZE 0x100000000
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#define PMEM_ADDR 0x1c0000000
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#define PMEM_SIZE 0x0c0000000
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