Rodrigo Arias Mallo
a8f3234031
The serial compatible string must be "ns16550" to be recognized by U-Boot.
160 lines
4.5 KiB
Plaintext
160 lines
4.5 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox";
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chosen {
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bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
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};
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cpus {
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x0000c350>;
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cpu@0 {
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clock-frequency = <0x02faf080>;
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device_type = "cpu";
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reg = <0x00000000>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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phandle = <0x00000004>;
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interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x00000005>;
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
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};
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reserved-memory {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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ranges;
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dma_pool@60000000 {
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reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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phandle = <0x00000001>;
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};
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dma_pool@70000000 {
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reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
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compatible = "shared-dma-pool";
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phandle = <0x00000006>;
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};
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};
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eth0_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00000000>;
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clock-frequency = <0x09502f90>;
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phandle = <0x00000002>;
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};
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pmem@1bff00000 {
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
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};
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pmem2@1b7f00000 {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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volatile;
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compatible = "pmem-region";
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reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
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};
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pmem3@f7e00000 {
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volatile;
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compatible = "pmem-region";
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reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
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};
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soc {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "BSC,Lagarto-bare-soc", "simple-bus";
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ranges;
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serial@40001000 {
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compatible = "ns16750";
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reg = <0x00000000 0x40001000 0x00000000 0x00000100>;
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interrupts = <0x00000000>;
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port-number = <0x00000000>;
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reg-shift = <0x00000002>;
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clock-frequency = <0x017d7840>;
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current-speed = <0x0001c200>;
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status = "okay";
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phandle = <0x00000007>;
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};
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ethernet0 {
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xlnx,rxmem = <0x000005f2>;
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carv,mtu = <0x000005dc>;
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carv,no-mac;
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device_type = "network";
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local-mac-address = [02 05 00 01 00 05];
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axistream-connected = <0x000000fe>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <0x00000001>;
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};
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dma@40020000 {
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xlnx,include-dre;
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phandle = <0x000000fe>;
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#dma-cells = <0x00000001>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <0x00000002 0x00000002 0x00000002 0x00000002>;
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reg = <0x00000000 0x40200000 0x00000000 0x00400000>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <0x00000003>;
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interrupts = <0x00000002 0x00000003>;
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xlnx,addrwidth = <0x00000028>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x00000017>;
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dma-channel@40020000 {
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0x00000001>;
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interrupts = <0x00000002>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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dma-channel@40020030 {
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <0x00000001>;
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interrupts = <0x00000003>;
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xlnx,datawidth = <0x00000040>;
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xlnx,device-id = <0x00000000>;
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xlnx,include-dre;
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};
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};
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clint@40002000 {
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reg-names = "control";
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interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
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compatible = "riscv,clint0";
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#interrupt-cells = <0x00000001>;
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reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
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};
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plic@fff1100000 {
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#address-cells = <0x00000000>;
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compatible = "riscv,plic0";
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#interrupt-cells = <0x00000001>;
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reg = <0x000000ff 0xf1100000 0x00000000 0x04000000>;
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riscv,ndev = <0x00000003>;
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riscv,max-priority = <0x00000007>;
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interrupt-controller;
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phandle = <0x00000003>;
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};
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};
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__symbols__ {
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CPU0 = "/cpus/cpu@0";
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CPU0_intc = "/cpus/cpu@0/interrupt-controller";
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eth_pool = "/reserved-memory/dma_pool@60000000";
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meep_pool = "/reserved-memory/dma_pool@70000000";
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eth0_clk = "/eth0_clk";
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uart0 = "/soc/serial@40001000";
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dma_eth = "/soc/dma@40020000";
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PLIC0 = "/soc/plic@fff1100000";
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};
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};
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