nixos-riscv/sa-fpga-crt.patch
2024-08-22 17:12:42 +02:00

16 lines
402 B
Diff

diff --git a/fpga_core_bridge/simulator/tests/c_tests/common/crt.S b/fpga_core_bridge/simulator/tests/c_tests/common/crt.S
index 3f5bb2c..bd738b1 100644
--- a/fpga_core_bridge/simulator/tests/c_tests/common/crt.S
+++ b/fpga_core_bridge/simulator/tests/c_tests/common/crt.S
@@ -59,10 +59,6 @@ _start:
#else
bltz t0, 1f
#endif
-2:
- li a0, 1
- sw a0, tohost, t0
- j 2b
1:
#ifdef __riscv_flen