439 lines
13 KiB
Diff
439 lines
13 KiB
Diff
diff --git a/include/sbi_utils/serial/alveo_uart.h b/include/sbi_utils/serial/alveo_uart.h
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new file mode 100644
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index 0000000..0b6408c
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--- /dev/null
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+++ b/include/sbi_utils/serial/alveo_uart.h
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@@ -0,0 +1,13 @@
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+/*
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+ * SPDX-License-Identifier: BSD-2-Clause
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+ */
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+
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+#ifndef __SERIAL_ALVEO_UART_H__
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+#define __SERIAL_ALVEO_UART_H__
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+
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+#include <sbi/sbi_types.h>
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+
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+int alveo_uart_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
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+ u32 reg_width, u32 reg_offset);
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+
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+#endif
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diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
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index e3589ca..b754c7c 100644
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--- a/lib/utils/serial/Kconfig
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+++ b/lib/utils/serial/Kconfig
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@@ -84,6 +84,10 @@ config SERIAL_UART8250
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bool "8250 UART support"
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default n
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+config SERIAL_ALVEO_UART
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+ bool "ALveo UART support"
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+ default n
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+
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config SERIAL_XILINX_UARTLITE
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bool "Xilinx UART Lite support"
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default n
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diff --git a/lib/utils/serial/alveo_uart.c b/lib/utils/serial/alveo_uart.c
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new file mode 100644
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index 0000000..a351741
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--- /dev/null
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+++ b/lib/utils/serial/alveo_uart.c
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@@ -0,0 +1,123 @@
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+/*
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+ * SPDX-License-Identifier: BSD-2-Clause
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+ */
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+
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+#include <sbi/riscv_io.h>
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+#include <sbi/sbi_console.h>
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+#include <sbi_utils/serial/alveo_uart.h>
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+
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+/* clang-format off */
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+
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+#define UART_RBR_OFFSET 0 /* In: Recieve Buffer Register */
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+#define UART_THR_OFFSET 0 /* Out: Transmitter Holding Register */
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+#define UART_DLL_OFFSET 0 /* Out: Divisor Latch Low */
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+#define UART_IER_OFFSET 1 /* I/O: Interrupt Enable Register */
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+#define UART_DLM_OFFSET 1 /* Out: Divisor Latch High */
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+#define UART_FCR_OFFSET 2 /* Out: FIFO Control Register */
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+#define UART_IIR_OFFSET 2 /* I/O: Interrupt Identification Register */
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+#define UART_LCR_OFFSET 3 /* Out: Line Control Register */
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+#define UART_MCR_OFFSET 4 /* Out: Modem Control Register */
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+#define UART_LSR_OFFSET 5 /* In: Line Status Register */
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+#define UART_MSR_OFFSET 6 /* In: Modem Status Register */
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+#define UART_SCR_OFFSET 7 /* I/O: Scratch Register */
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+#define UART_MDR1_OFFSET 8 /* I/O: Mode Register */
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+
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+#define UART_LSR_FIFOE 0x80 /* Fifo error */
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+#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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+#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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+#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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+#define UART_LSR_FE 0x08 /* Frame error indicator */
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+#define UART_LSR_PE 0x04 /* Parity error indicator */
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+#define UART_LSR_OE 0x02 /* Overrun error indicator */
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+#define UART_LSR_DR 0x01 /* Receiver data ready */
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+#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
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+
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+/* clang-format on */
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+
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+static volatile char *alveo_uart_base;
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+static u32 alveo_uart_in_freq;
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+static u32 alveo_uart_baudrate;
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+static u32 alveo_uart_reg_width;
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+static u32 alveo_uart_reg_shift;
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+
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+static u32 get_reg(u32 num)
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+{
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+ u32 offset = num << alveo_uart_reg_shift;
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+
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+ if (alveo_uart_reg_width == 1)
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+ return readb(alveo_uart_base + offset);
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+ else if (alveo_uart_reg_width == 2)
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+ return readw(alveo_uart_base + offset);
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+ else
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+ return readl(alveo_uart_base + offset);
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+}
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+
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+static void set_reg(u32 num, u32 val)
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+{
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+ u32 offset = num << alveo_uart_reg_shift;
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+
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+ if (alveo_uart_reg_width == 1)
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+ writeb(val, alveo_uart_base + offset);
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+ else if (alveo_uart_reg_width == 2)
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+ writew(val, alveo_uart_base + offset);
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+ else
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+ writel(val, alveo_uart_base + offset);
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+}
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+
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+static void alveo_uart_putc(char ch)
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+{
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+ while (!(get_reg(UART_LSR_OFFSET) & UART_LSR_TEMT))
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+ ;
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+
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+ set_reg(UART_THR_OFFSET, ch);
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+}
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+
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+static int alveo_uart_getc(void)
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+{
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+ if (get_reg(UART_LSR_OFFSET) & UART_LSR_DR)
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+ return get_reg(UART_RBR_OFFSET);
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+ return -1;
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+}
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+
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+static struct sbi_console_device alveo_uart_console = {
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+ .name = "alveo_uart",
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+ .console_putc = alveo_uart_putc,
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+ .console_getc = alveo_uart_getc
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+};
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+
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+int alveo_uart_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
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+ u32 reg_width, u32 reg_offset)
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+{
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+ u16 bdiv = 0;
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+
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+ alveo_uart_base = (volatile char *)base + reg_offset;
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+ alveo_uart_reg_shift = reg_shift;
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+ alveo_uart_reg_width = reg_width;
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+ alveo_uart_in_freq = in_freq;
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+ alveo_uart_baudrate = baudrate;
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+
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+ if (alveo_uart_baudrate) {
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+ bdiv = alveo_uart_in_freq / (16 * alveo_uart_baudrate);
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+ }
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+
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+ /* Disable all interrupts */
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+ set_reg(UART_IER_OFFSET, 0x00);
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+ /* Enable DLAB */
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+ set_reg(UART_LCR_OFFSET, 0x80);
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+
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+ if (bdiv) {
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+ /* Set divisor low byte */
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+ set_reg(UART_DLL_OFFSET, bdiv & 0xff);
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+ /* Set divisor high byte */
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+ set_reg(UART_DLM_OFFSET, (bdiv >> 8) & 0xff);
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+ }
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+
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+ /* 8 bits, no parity, one stop bit */
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+ set_reg(UART_LCR_OFFSET, 0x03); // previous was 0x0B
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+ /* Disable all interrupts*/
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+ set_reg(UART_IER_OFFSET, 0x00);
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+
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+ sbi_console_set_device(&alveo_uart_console);
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+
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+ return 0;
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+}
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diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
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index 1e6bd2e..0268bdf 100644
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--- a/lib/utils/serial/objects.mk
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+++ b/lib/utils/serial/objects.mk
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@@ -44,5 +44,6 @@ libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
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libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
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libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
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libsbiutils-objs-$(CONFIG_SERIAL_UART8250) += serial/uart8250.o
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+libsbiutils-objs-$(CONFIG_SERIAL_ALVEO_UART) += serial/alveo_uart.o
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libsbiutils-objs-$(CONFIG_SERIAL_XILINX_UARTLITE) += serial/xlnx-uartlite.o
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libsbiutils-objs-$(CONFIG_SERIAL_SEMIHOSTING) += serial/semihosting.o
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diff --git a/platform/fpga/sargantana_alveo/Kconfig b/platform/fpga/sargantana_alveo/Kconfig
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new file mode 100644
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index 0000000..bf3e7e6
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--- /dev/null
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+++ b/platform/fpga/sargantana_alveo/Kconfig
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@@ -0,0 +1,10 @@
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+# SPDX-License-Identifier: BSD-2-Clause
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+
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+config PLATFORM_SARGANTANA_ALVEO_FPGA
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+ bool
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+ select FDT
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+ select IPI_MSWI
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+ select IRQCHIP_PLIC
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+ select SERIAL_ALVEO_UART
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+ select TIMER_MTIMER
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+ default y
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diff --git a/platform/fpga/sargantana_alveo/configs/defconfig b/platform/fpga/sargantana_alveo/configs/defconfig
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new file mode 100644
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index 0000000..e69de29
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diff --git a/platform/fpga/sargantana_alveo/objects.mk b/platform/fpga/sargantana_alveo/objects.mk
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new file mode 100644
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index 0000000..d444abe
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--- /dev/null
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+++ b/platform/fpga/sargantana_alveo/objects.mk
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@@ -0,0 +1,87 @@
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+#
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+# SPDX-License-Identifier: BSD-2-Clause
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+#
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+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
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+#
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+
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+# Compiler pre-processor flags
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+platform-cppflags-y =
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+
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+# C Compiler and assembler flags.
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+platform-cflags-y =
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+platform-asflags-y =
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+
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+# Linker flags: additional libraries and object files that the platform
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+# code needs can be added here
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+platform-ldflags-y =
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+
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+#
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+# Command for platform specific "make run"
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+# Useful for development and debugging on plaftform simulator (such as QEMU)
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+#
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+# platform-runcmd = your_platform_run.sh
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+
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+#
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+# Platform RISC-V XLEN, ABI, ISA and Code Model configuration.
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+# These are optional parameters but platforms can optionaly provide it.
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+# Some of these are guessed based on GCC compiler capabilities
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+#
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+PLATFORM_RISCV_XLEN = 64
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+PLATFORM_RISCV_ABI = lp64d
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+PLATFORM_RISCV_ISA = rv64imafd
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+PLATFORM_RISCV_CODE_MODEL = medany
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+
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+# Space separated list of object file names to be compiled for the platform
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+platform-objs-y += platform.o
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+
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+#
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+# If the platform support requires a builtin device tree file, the name of
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+# the device tree compiled file should be specified here. The device tree
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+# source file be in the form <dt file name>.dts
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+#
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+# platform-objs-y += <dt file name>.o
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+
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+# Firmware load address configuration. This is mandatory.
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+FW_TEXT_START=0x80000000
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+
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+# Optional parameter for path to external FDT
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+# FW_FDT_PATH="path to platform flattened device tree file"
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+
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+#
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+# Dynamic firmware configuration.
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+# Optional parameters are commented out. Uncomment and define these parameters
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+# as needed.
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+#
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+FW_DYNAMIC=n
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+
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+#
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+# Jump firmware configuration.
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+# Optional parameters are commented out. Uncomment and define these parameters
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+# as needed.
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+#
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+FW_JUMP=n
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+# This needs to be 4MB aligned for 32-bit support
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+# This needs to be 2MB aligned for 64-bit support
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+# ifeq ($(PLATFORM_RISCV_XLEN), 32)
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+# FW_JUMP_ADDR=0x80400000
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+# else
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+# FW_JUMP_ADDR=0x80200000
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+# endif
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+# FW_JUMP_FDT_ADDR=0x82200000
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+
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+#
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+# Firmware with payload configuration.
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+# Optional parameters are commented out. Uncomment and define these parameters
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+# as needed.
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+#
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+FW_PAYLOAD=y
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+# This needs to be 4MB aligned for 32-bit support
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+# This needs to be 2MB aligned for 64-bit support
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+ifeq ($(PLATFORM_RISCV_XLEN), 32)
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+FW_PAYLOAD_OFFSET=0x400000
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+else
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+FW_PAYLOAD_OFFSET=0x200000
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+endif
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+FW_PAYLOAD_ALIGN=0x1000
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+# FW_PAYLOAD_PATH="path to next boot stage binary image file"
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+# FW_PAYLOAD_FDT_ADDR=0x82200000
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diff --git a/platform/fpga/sargantana_alveo/platform.c b/platform/fpga/sargantana_alveo/platform.c
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new file mode 100644
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index 0000000..a359b34
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--- /dev/null
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+++ b/platform/fpga/sargantana_alveo/platform.c
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@@ -0,0 +1,146 @@
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+/*
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+ * SPDX-License-Identifier: BSD-2-Clause
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+ *
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+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
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+ */
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+
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+#include <sbi/riscv_asm.h>
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+#include <sbi/riscv_encoding.h>
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+#include <sbi/sbi_const.h>
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+#include <sbi/sbi_platform.h>
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+
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+/*
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+ * Include these files as needed.
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+ * See objects.mk SARGANTANA_ALVEO_xxx configuration parameters.
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+ */
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+
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+#include <sbi_utils/serial/alveo_uart.h>
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+#include <sbi/sbi_timer.h>
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+
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+#define SARGANTANA_ALVEO_HART_COUNT 1
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+
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+#define SARGANTANA_ALVEO_UART_BASE_ADDR 0x40000000
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+#define SARGANTANA_ALVEO_UART_OFFSET 0x1000
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+//#define SARGANTANA_ALVEO_UART_ADDR SARGANTANA_ALVEO_UART_BASE_ADDR + SARGANTANA_ALVEO_UART_XLNX_OFFSET
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+#define SARGANTANA_ALVEO_UART_INPUT_FREQ 50000000
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+#define SARGANTANA_ALVEO_UART_BAUDRATE 115200
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+
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+#define SARGANTANA_ALVEO_TIMER_BASE 0x40170000
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+#define ADDR_TIME_L 0x0u // 32 lower bits of the time register
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+#define ADDR_TIME_H 0x1u // 32 higher bits of the time register
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+#define ADDR_TIMECMP_L 0x2u // 32 lower bits of the time comparator
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+#define ADDR_TIMECMP_H 0x3u // 32 higher bits of the time comparator
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+
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+volatile uint32_t *timer_base_ptr = (uint32_t *)(SARGANTANA_ALVEO_TIMER_BASE);
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+
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+/*
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+ * Platform early initialization.
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+ */
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+static int sargantana_alveo_early_init(bool cold_boot)
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+{
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+ return 0;
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+}
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+
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+/*
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+ * Platform final initialization.
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+ */
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+static int sargantana_alveo_final_init(bool cold_boot)
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+{
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+ return 0;
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+}
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+
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+/*
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+ * Initialize the platform console.
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+ */
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+static int sargantana_alveo_console_init(void)
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+{
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+ return alveo_uart_init(SARGANTANA_ALVEO_UART_BASE_ADDR,
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+ SARGANTANA_ALVEO_UART_INPUT_FREQ,
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+ SARGANTANA_ALVEO_UART_BAUDRATE,
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+ 2, 4,
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+ SARGANTANA_ALVEO_UART_OFFSET);
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+}
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+
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+/*
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+ * Initialize the platform interrupt controller for current HART.
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+ */
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+static int sargantana_alveo_irqchip_init(bool cold_boot)
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+{
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+ u32 hartid = current_hartid();
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+ return hartid;
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+}
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+
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+/*
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+ * Initialize IPI for current HART.
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+ */
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+static int sargantana_alveo_ipi_init(bool cold_boot)
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+{
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+ return 0;
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+}
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+
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+/*
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+ * Get platform timer value.
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+ */
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+static u64 sargantana_alveo_timer_value(void)
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+{
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+ return ((u64)*(timer_base_ptr + ADDR_TIME_H) << 32) + *(timer_base_ptr + ADDR_TIME_L);
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+}
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+
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+/*
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+ * Start platform timer event for current HART.
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+ */
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+static void sargantana_alveo_timer_event_start(u64 next_event)
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+{
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+ *(timer_base_ptr + ADDR_TIMECMP_H) = next_event >> 32;
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+ *(timer_base_ptr + ADDR_TIMECMP_L) = next_event;
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+}
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+
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+/*
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+ * Stop platform timer event for current HART.
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+ */
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+static void sargantana_alveo_timer_event_stop(void)
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+{
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+
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+ *(timer_base_ptr + ADDR_TIMECMP_H) = 0;
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+ *(timer_base_ptr + ADDR_TIMECMP_L) = 0;
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+}
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+
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+static struct sbi_timer_device mtimer = {
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+ .name = "generic_timer", // TODO Where the timer comes from? I would prefer a better name :p
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+ .timer_freq = SARGANTANA_ALVEO_UART_INPUT_FREQ,
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+ .timer_value = sargantana_alveo_timer_value,
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+ .timer_event_start = sargantana_alveo_timer_event_start,
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+ .timer_event_stop = sargantana_alveo_timer_event_stop
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+};
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+
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+/*
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+ * Initialize platform timer for current HART.
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+ */
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+static int sargantana_alveo_timer_init(bool cold_boot)
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+{
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+ *(timer_base_ptr + ADDR_TIMECMP_H) = 0;
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+ *(timer_base_ptr + ADDR_TIMECMP_L) = 0;
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+ sbi_timer_set_device(&mtimer);
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+ return 0;
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+}
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+
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+/*
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+ * Platform descriptor.
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+ */
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+const struct sbi_platform_operations sargantana_alveo_ops = {
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+ .early_init = sargantana_alveo_early_init,
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+ .final_init = sargantana_alveo_final_init,
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+ .console_init = sargantana_alveo_console_init,
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+ .irqchip_init = sargantana_alveo_irqchip_init,
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+ .ipi_init = sargantana_alveo_ipi_init,
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+ .timer_init = sargantana_alveo_timer_init
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+};
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+const struct sbi_platform platform = {
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+ .opensbi_version = OPENSBI_VERSION,
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+ .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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+ .name = "Sargantana (for Xilinx Alveo FPGA)",
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+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
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+ .hart_count = SARGANTANA_ALVEO_HART_COUNT,
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+ .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
|
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+ .platform_ops_addr = (unsigned long)&sargantana_alveo_ops
|
|
+};
|