256 lines
6.9 KiB
Plaintext
256 lines
6.9 KiB
Plaintext
#include "lagarto_ox.h"
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>; /* 64 bits memory addresses */
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compatible = "riscv,rv64i";
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model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <RTC_FREQ>;
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CPU0: cpu@0 {
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clock-frequency = <CPU_FREQ>;
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafd";
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mmu-type = "riscv,sv39";
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tlb-split;
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i-cache-block-size = <64>; // Guess
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i-cache-sets = <4>;
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i-cache-size = <16384>;
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i-tlb-sets = <1>; // Guess
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i-tlb-size = <32>; // Guess
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d-cache-block-size = <64>; // Guess
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d-cache-sets = <4>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>; // Guess
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d-tlb-size = <32>; // Guess
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/* Hart-Level Interrupt Controller: Every interrupt is
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* ultimately routed through a hart's HLIC before it
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* interrupts that hart. */
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HLIC0: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller; /* Receives interrupts */
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compatible = "riscv,cpu-intc";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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};
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};
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};
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memory@MEM_ADDR {
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device_type = "memory";
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reg = /bits/ 64 <MEM_ADDR MEM_SIZE>;
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};
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reserved-memory {
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#address-cells = <2>; /* Starting address and size */
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#size-cells = <2>; /* 64 bits memory addresses */
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ranges;
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eth_pool: dma_pool@ETHPOOL_ADDR {
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reg = /bits/ 64 <ETHPOOL_ADDR ETHPOOL_SIZE>;
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compatible = "shared-dma-pool";
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};
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onic_pool: dma_pool@ONICPOOL_ADDR {
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reg = /bits/ 64 <ONICPOOL_ADDR ONICPOOL_SIZE>;
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compatible = "shared-dma-pool";
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};
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};
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pmem@PMEM_ADDR {
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/* volatile; This property indicates that this region is
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* actually backed by non-persistent memory. This lets the OS
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* know that it may skip the cache flushes required to ensure
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* data is made persistent after a write. */
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volatile;
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compatible = "pmem-region";
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reg = /bits/ 64 <PMEM_ADDR PMEM_SIZE>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "BSC,Lagarto-ox-soc", "simple-bus";
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ranges;
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/* For bitstream e97dd7b2-397f-11ef-abe0-bbd201a5a630 with two
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* consoles */
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#ifdef ENABLE_UART0
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/* The serial for the kernel console */
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uart_console: serial@UART0_ADDR {
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compatible = "ns16550";
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reg = /bits/ 64 <UART0_ADDR UART0_SIZE>;
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reg-shift = <2>;
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/* No interrupts for this UART, use console=hvc0 */
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/* This clock is the SERIAL_CLK */
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clock-frequency = <CPU_FREQ>;
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current-speed = <UART0_SPEED>;
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status = "okay";
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};
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#endif /* ENABLE_UART0 */
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#ifdef ENABLE_UART1
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/* The serial for interrupt tests */
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uart_testing: serial@UART1_ADDR {
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compatible = "ns16550";
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reg = /bits/ 64 <UART1_ADDR UART1_SIZE>;
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reg-shift = <2>;
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/* Output interrupt 1 (the first one) */
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interrupts = <1>;
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interrupt-parent = <&PLIC>;
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clock-frequency = <CPU_FREQ>;
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current-speed = <UART1_SPEED>;
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status = "okay";
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};
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#endif /* ENABLE_UART1 */
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#ifdef ENABLE_ETHERNET
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ethernet0 {
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xlnx,rxmem = <1522>;
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carv,mtu = <1500>;
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carv,no-mac;
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device_type = "network";
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// 02:$node:00:01:00:$fpga -> 02:05:00:01:00:02
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// 10.5.1.$N/16 -> 10.5.1.184/16
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// N = 150 + ($node - 1) * 8 + $fpga
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local-mac-address = [00 00 00 00 00 00];
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axistream-connected = <&axi_dma>;
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compatible = "xlnx,xxv-ethernet-1.0-carv";
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memory-region = <ð_pool>;
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};
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#endif /* ENABLE_ETHERNET */
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#ifdef ENABLE_AXIDMA
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dma_clk: dma_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <AXIDMA_FREQ>;
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};
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axi_dma: dma@AXIDMA_ADDR {
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reg = /bits/ 64 <AXIDMA_ADDR AXIDMA_SIZE>;
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reg-shift = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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xlnx,include-dre;
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#dma-cells = <0x1>;
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compatible = "xlnx,axi-dma-1.00.a";
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clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
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"m_axi_s2mm_aclk", "m_axi_sg_aclk";
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clocks = <&dma_clk>, <&dma_clk>, <&dma_clk>, <&dma_clk>;
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interrupt-names = "mm2s_introut", "s2mm_introut";
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interrupt-parent = <&PLIC>;
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interrupts = <2 3>;
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xlnx,addrwidth = <0x28>;
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xlnx,include-sg;
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xlnx,sg-length-width = <0x17>;
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dma-channel@AXIDMA_CH0 {
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reg = /bits/ 64 <AXIDMA_CH0 0x30>;
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compatible = "xlnx,axi-dma-mm2s-channel";
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dma-channels = <0>;
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interrupts = <2>;
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xlnx,datawidth = <0x40>;
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xlnx,device-id = <0x0>;
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xlnx,include-dre;
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};
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dma-channel@AXIDMA_CH1 {
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reg = /bits/ 64 <AXIDMA_CH1 0x30>;
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compatible = "xlnx,axi-dma-s2mm-channel";
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dma-channels = <1>;
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interrupts = <3>;
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xlnx,datawidth = <0x40>;
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xlnx,device-id = <0x0>;
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xlnx,include-dre;
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};
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};
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#endif /* ENABLE_AXIDMA */
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#ifdef ENABLE_PLIC
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/* Platform-Level Interrupt Controller: Delivers interrupts to
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* HARTs. */
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PLIC: plic@PLIC_ADDR {
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reg = /bits/ 64 <PLIC_ADDR PLIC_SIZE>;
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compatible = "riscv,plic0";
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interrupt-controller; /* Receives interrupts */
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#address-cells = <0>;
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#interrupt-cells = <1>;
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/* Sends interrupts to HART interrupt controllers.
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* Configures two output targets or contexts:
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* - context 0: machine mode external interrupt (11)
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* - context 1: supervisor mode external interrupt (9)
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*/
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interrupts-extended = <&HLIC0 11>, <&HLIC0 9>;
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riscv,ndev = <PLIC_NDEV>;
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//riscv,max-priority = <0x7>;
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};
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#endif /* ENABLE_PLIC */
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#ifdef ENABLE_CLINT
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/* Core Local Interruptor: It directly connects to the timer and
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* inter-processor interrupt lines of various HARTs (or CPUs) so
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* RISC-V per-HART (or per-CPU) local interrupt controller is
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* the parent interrupt controller for CLINT device. The clock
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* frequency of CLINT is specified via "timebase-frequency" DT
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* property of "/cpus" DT node. The "timebase-frequency" DT
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* property is described in
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* Documentation/devicetree/bindings/riscv/cpus.yaml
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*/
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clint: clint@CLINT_ADDR {
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reg = /bits/ 64 <CLINT_ADDR CLINT_SIZE>;
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reg-names = "control";
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interrupts-extended = <&HLIC0 3>, <&HLIC0 7>;
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compatible = "riscv,clint0";
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};
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#endif /* ENABLE_CLINT */
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#if 0
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/* There is another auxiliar clint (timer) at 40010000 for
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* tests, but we don't tell the kernel so we can use it for
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* testing interrupts manually. */
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aux_timer: clint@AUXTIMER_ADDR {
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reg = /bits/ 64 <AUXTIMER_ADDR AUXTIMER_SIZE>;
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reg-names = "control";
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interrupts = <4>; /* PLIC input source 4 */
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interrupt-parent = <&PLIC>;
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compatible = "riscv,clint0";
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};
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#endif
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#ifdef ENABLE_SPI
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serial@UART2_ADDR {
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compatible = "ns16750";
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reg = /bits/ 64 <UART2_ADDR UART2_SIZE>;
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interrupt-parent = <&PLIC>;
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interrupts = <5>;
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clock-frequency = <CPU_FREQ>;
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current-speed = <UART2_SPEED>;
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status = "okay";
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};
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spi@SPI_ADDR {
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compatible = "ti,keystone-spi";
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reg = /bits/ 64 <SPI_ADDR SPI_SIZE>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&PLIC>;
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interrupt-names = "intvec0", "intvec1";
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interrupts = <6 0>, <7 0>;
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ti,davinci-spi-intr-line = <0>;
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spi-max-frequency = <24000000>;
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loopback-mode = <1>;
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status = "okay";
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};
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#endif /* ENABLE_SPI */
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};
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};
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