#define CPU_FREQ	50000000 /* 50 MHz */
/* FIXME: The real RTC frequency is around half that, as the divider was wrongly
 * configured. So for now lets use the real frequency:
 *   50e6 / (1525*2) = 16393.44262295082 -> 16393 Hz */
#define RTC_FREQ	16393

/* Memory layout:
 *
 * [0x0_4000_0000, 0x0_6000_0000) -> IO       (512 MiB)
 * [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB)
 * [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB)
 * [0x0_8000_0000, 0x1_8000_0000) -> RAM memory (4 GiB)
 * [0x1_8000_0000, 0x1_c000_0000) -> Unused     (1 GiB)
 * [0x1_c000_0000, 0x2_8000_0000) -> PMEM       (3 GiB)
 */

#define UART0_SPEED	115200
#define UART0_ADDR	0x40001000
#define UART0_SIZE	0x00001000

#define UART1_SPEED	UART0_SPEED
#define UART1_ADDR	0x40003000
#define UART1_SIZE	0x00001000

#define AUXTIMER_ADDR	0x40010000
#define AUXTIMER_SIZE	0x00010000

#define CLINT_ADDR	0x40100000
#define CLINT_SIZE	0x00010000

#define AXIDMA_ADDR	0x40400000
#define AXIDMA_SIZE	0x00400000
#define AXIDMA_CH0	0x40400000
#define AXIDMA_CH1	0x40400030
#define AXIDMA_FREQ	156250000

#define PLIC_ADDR	0x40800000
#define PLIC_SIZE	0x00400000
#define PLIC_NDEV	4

#define ETHPOOL_ADDR	0x60000000
#define ETHPOOL_SIZE	0x10000000

#define ONICPOOL_ADDR	0x70000000
#define ONICPOOL_SIZE	0x10000000

/* Notice addresses > 32 bits from here */

#define MEM_ADDR	0x080000000
#define MEM_SIZE	0x100000000

#define PMEM_ADDR	0x1c0000000
#define PMEM_SIZE	0x0c0000000

/* Toggles */

#define ENABLE_UART0
#define ENABLE_UART1
#define ENABLE_ETHERNET
#define ENABLE_AXIDMA
#define ENABLE_PLIC
#define ENABLE_CLINT
//#define ENABLE_SPI