/dts-v1/; / { #address-cells = <2>; #size-cells = <2>; /* 64 bits memory addresses */ compatible = "riscv,rv64i"; model = "Barcelona Supercomputing Center - Lagarto Ox (NixOS)"; // chosen { // bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash"; // }; cpus { #address-cells = <1>; #size-cells = <0>; /* Timer */ timebase-frequency = <50000>; /* 50 kHz */ CPU0: cpu@0 { clock-frequency = <50000000>; /* 50 MHz */ device_type = "cpu"; reg = <0>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafd"; mmu-type = "riscv,sv39"; tlb-split; phandle = <0x00000004>; /* Hart-Level Interrupt Controller: Every interrupt is * ultimately routed through a hart's HLIC before it * interrupts that hart. */ HLIC0: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; /* Receives interrupts */ compatible = "riscv,cpu-intc"; phandle = <0x5>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; }; }; }; /* Memory layout: * * [0x0_6000_0000, 0x0_7000_0000) -> DMA pool (256 MiB) * [0x0_7000_0000, 0x0_8000_0000) -> DMA pool (256 MiB) * [0x0_8000_0000, 0x0_fff0_0000) -> RAM memory (2047 MiB) * [0x0_fff0_0000, 0x1_0000_0000) -> Empty (1 MiB) * [0x1_0000_0000, 0x1_c000_0000) -> PMEM (3072 MiB) * [0x1_c000_0000, 0x2_8000_0000) -> Empty (3072 MiB) */ memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x7ff00000>; }; reserved-memory { #address-cells = <2>; /* Starting address and size */ #size-cells = <2>; /* 64 bits memory addresses */ ranges; eth_pool: dma_pool@60000000 { reg = <0x0 0x60000000 0x0 0x10000000>; compatible = "shared-dma-pool"; }; onic_pool: dma_pool@70000000 { reg = <0x0 0x70000000 0x0 0x10000000>; compatible = "shared-dma-pool"; }; }; // eth0_clk: eth0_clk { // compatible = "fixed-clock"; // #clock-cells = <0x00000000>; // clock-frequency = <0x09502f90>; // phandle = <0x00000002>; // }; pmem@100000000 { /* volatile; This property indicates that this region is * actually backed by non-persistent memory. This lets the OS * know that it may skip the cache flushes required to ensure * data is made persistent after a write. */ volatile; compatible = "pmem-region"; reg = <0x1 0x00000000 0x0 0xc0000000>; }; soc { #address-cells = <0x00000002>; #size-cells = <0x00000002>; compatible = "BSC,Lagarto-ox-soc", "simple-bus"; ranges; SERIAL: serial@40001000 { compatible = "ns16550"; reg = <0x0 0x40001000 0x0 0x100>; interrupts = <1>; /* Output interrupt 1 */ interrupt-parent = <&PLIC>; reg-shift = <2>; /* This clock is the SERIAL_CLK */ clock-frequency = <50000000>; current-speed = <115200>; status = "okay"; }; // ethernet0 { // xlnx,rxmem = <0x000005f2>; // carv,mtu = <0x000005dc>; // carv,no-mac; // device_type = "network"; // local-mac-address = [02 05 00 01 00 05]; // axistream-connected = <0x000000fe>; // compatible = "xlnx,xxv-ethernet-1.0-carv"; // memory-region = <ð_pool>; // }; // dma@40400000 { // xlnx,include-dre; // phandle = <0x000000fe>; // #dma-cells = <0x00000001>; // compatible = "xlnx,axi-dma-1.00.a"; // clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk"; // clocks = <ð0_clk>, <ð0_clk>, <ð0_clk>, <ð0_clk>; // reg = <0x00000000 0x40400000 0x00000000 0x00400000>; // interrupt-names = "mm2s_introut", "s2mm_introut"; // interrupt-parent = <&PLIC>; // interrupts = <2 3>; // xlnx,addrwidth = <0x00000028>; // xlnx,include-sg; // xlnx,sg-length-width = <0x00000017>; // dma-channel@40400000 { // compatible = "xlnx,axi-dma-mm2s-channel"; // dma-channels = <0x00000000>; // interrupts = <0x00000002>; // xlnx,datawidth = <0x00000040>; // xlnx,device-id = <0x00000000>; // xlnx,include-dre; // }; // dma-channel@40400030 { // compatible = "xlnx,axi-dma-s2mm-channel"; // dma-channels = <0x00000001>; // interrupts = <0x00000003>; // xlnx,datawidth = <0x00000040>; // xlnx,device-id = <0x00000000>; // xlnx,include-dre; // }; // }; /* Platform-Level Interrupt Controller: Delivers interrupts to * HARTs. */ PLIC: plic@40800000 { compatible = "riscv,plic0"; interrupt-controller; /* Receives interrupts */ #address-cells = <0>; #interrupt-cells = <1>; /* Sends interrupts to HART interrupt controllers */ /* * From: linux-6.6.1/arch/riscv/include/asm/csr.h * * Interrupt causes (minus the high bit) * #define IRQ_S_SOFT 1 * #define IRQ_VS_SOFT 2 * #define IRQ_M_SOFT 3 * #define IRQ_S_TIMER 5 * #define IRQ_VS_TIMER 6 * #define IRQ_M_TIMER 7 * #define IRQ_S_EXT 9 * #define IRQ_VS_EXT 10 * #define IRQ_M_EXT 11 * #define IRQ_S_GEXT 12 * #define IRQ_PMU_OVF 13 * #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) * #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) */ interrupts-extended = <&HLIC0 9>, <&HLIC0 11>; reg = < 0x0 0x40800000 0x0 0x00400000>; riscv,ndev = <3>; //riscv,max-priority = <0x7>; phandle = <0x3>; }; /* Core Local Interruptor: It directly connects to the timer and * inter-processor interrupt lines of various HARTs (or CPUs) so * RISC-V per-HART (or per-CPU) local interrupt controller is * the parent interrupt controller for CLINT device. The clock * frequency of CLINT is specified via "timebase-frequency" DT * property of "/cpus" DT node. The "timebase-frequency" DT * property is described in * Documentation/devicetree/bindings/riscv/cpus.yaml */ timer@40002000 { reg = <0x0 0x40002000 0x0 0x000c0000>; reg-names = "control"; interrupts-extended = <&HLIC0 3>, <&HLIC0 7>; /*<&CPU0 0x3>, <&CPU0 0x7>,*/ /*<&onic_pool 0x3>, <&onic_pool 0x7>,*/ /*<&SERIAL 0x3>, <&SERIAL 0x7>*/ compatible = "riscv,clint0"; }; /* Guesswork: There must be a timer at 0x40170000 as it is * initialized in OpenSBI. It seems to drive the console. */ //SERIAL_CLK: timer@40170000 { // clock-frequency = <100000000>; // clocks = <&clk_bus_0>; // compatible = "xlnx,xps-timer-1.00.a"; // interrupt-parent = <&axi_intc_1>; // interrupts = <2 2>; // reg = <0x41c00000 0x10000>; // xlnx,count-width = <0x20>; // xlnx,one-timer-only = <0x0>; //}; }; };