/dts-v1/;
/ {
	#address-cells = <0x00000002>;
	#size-cells = <0x00000002>;
	compatible = "riscv,rv64i";
	model = "Barcelona Supercomputing Center - Lagarto Ox";
	chosen {
			bootargs = "earlyprintk ignore_loglevel earlycon=sbi console=hvc0 root=/dev/pmem0p1 ro init=/bin/bash";
	};
	cpus {
			#address-cells = <0x00000001>;
			#size-cells = <0x00000000>;
			timebase-frequency = <0x0000c350>;
			cpu@0 {
					clock-frequency = <0x02FAF080>;
					device_type = "cpu";
					reg = <0x00000000>;
					status = "okay";
					compatible = "riscv";
					riscv,isa = "rv64imafd";
					mmu-type = "riscv,sv39";
					tlb-split;
					L3: interrupt-controller {
							#interrupt-cells = <0x00000001>;
							interrupt-controller;
							compatible = "riscv,cpu-intc";
					};
			};
	};
	memory@80000000 {
			device_type = "memory";
			reg = <0x00000000 0x80000000 0x00000000 0x77e00000>;
	};
	reserved-memory {
			#address-cells = <0x00000002>;
			#size-cells = <0x00000002>;
			ranges;
			eth_pool: dma_pool@60000000 {
					reg = <0x00000000 0x60000000 0x00000000 0x10000000>;
					compatible = "shared-dma-pool";
			};
			onic_pool: dma_pool@70000000 {
					reg = <0x00000000 0x70000000 0x00000000 0x10000000>;
					compatible = "shared-dma-pool";
			};
	};
	eth0_clk: eth0_clk {
			compatible = "fixed-clock";
			#clock-cells = <0x00000000>;
			clock-frequency = <0x09502f90>;
	};
	pmem@1bff00000 {
			volatile;
			compatible = "pmem-region";
			reg = <0x00000001 0xbff00000 0x00000000 0xc0100000>;
	};
	pmem2@1b7f00000 {
			#address-cells = <0x00000002>;
			#size-cells = <0x00000002>;
			volatile;
			compatible = "pmem-region";
			reg = <0x00000001 0xb7f00000 0x00000000 0x08000000>;
	};
	pmem3@f7e00000 {
			volatile;
			compatible = "pmem-region";
			reg = <0x00000000 0xf7e00000 0x00000000 0xc0100000>;
	};
	soc {
			#address-cells = <0x00000002>;
			#size-cells = <0x00000002>;
			compatible = "BSC,Lagarto-bare-soc", "simple-bus";
			ranges;
			serial@40001000 {
					compatible = "ns16750";
					reg = <0x00000000 0x40001000 0x00000000 0x00001000>;
					interrupts = <0x00000000>;
					port-number = <0x00000000>;
					reg-shift = <0x00000002>;
					clock-frequency = <0x02FAF080>;
					current-speed = <0x0001c200>;
					status = "okay";
			};
			ethernet0 {
					xlnx,rxmem = <0x000005f2>;
					carv,mtu = <0x000005dc>;
					carv,no-mac;
					device_type = "network";
					local-mac-address = [02 05 00 01 00 05];
					axistream-connected = <0x000000fe>;
					compatible = "xlnx,xxv-ethernet-1.0-carv";
					memory-region = <&eth_pool>;
			};
			dma@40400000 {
					xlnx,include-dre;
					phandle = <0x000000fe>;
					#dma-cells = <0x00000001>;
					compatible = "xlnx,axi-dma-1.00.a";
					clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
					clocks = <&eth0_clk>, <&eth0_clk>, <&eth0_clk>, <&eth0_clk>;
					reg = <0x00000000 0x40400000 0x00000000 0x00400000>;
					interrupt-names = "mm2s_introut", "s2mm_introut";
					interrupt-parent = <&PLIC0>;
					interrupts = <0x00000002 0x00000003>;
					xlnx,addrwidth = <0x00000028>;
					xlnx,include-sg;
					xlnx,sg-length-width = <0x00000017>;
					dma-channel@40400000 {
							compatible = "xlnx,axi-dma-mm2s-channel";
							dma-channels = <0x00000000>;
							interrupts = <0x00000002>;
							xlnx,datawidth = <0x00000040>;
							xlnx,device-id = <0x00000000>;
							xlnx,include-dre;
					};
					dma-channel@40400030 {
							compatible = "xlnx,axi-dma-s2mm-channel";
							dma-channels = <0x00000001>;
							interrupts = <0x00000003>;
							xlnx,datawidth = <0x00000040>;
							xlnx,device-id = <0x00000000>;
							xlnx,include-dre;
					};
			};
			clint@40002000 {
					reg-names = "control";
					interrupts-extended = <0x00000004 0x00000003 0x00000004 0x00000007 0x00000005 0x00000003 0x00000005 0x00000007 0x00000006 0x00000003 0x00000006 0x00000007 0x00000007 0x00000003 0x00000007 0x00000007>;
					compatible = "riscv,clint0";
					#interrupt-cells = <0x00000001>;
					reg = <0x00000000 0x40002000 0x00000000 0x000c0000>;
			};
			PLIC0: plic@40800000 {
				    #interrupt-cells = <1>;
					compatible = "riscv,plic0";
					interrupt-controller;
					interrupts-extended = <&L3 3 &L3 7>;
					reg = < 0x00000000 0x40800000 0x00000000 0x00400000>;
					riscv,ndev = <0x00000003>;
					riscv,max-priority = <0x00000007>;
			};
	};

};