Rodrigo Arias Mallo
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706d858347
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Claim aux timer interrupt
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2024-08-21 11:39:45 +02:00 |
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Rodrigo Arias Mallo
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ea081176f7
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Clear MIP before enabling interrupts
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2024-08-21 10:20:11 +02:00 |
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Rodrigo Arias Mallo
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2f28f9268a
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Enable machine interrupts
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2024-08-21 10:13:45 +02:00 |
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Rodrigo Arias Mallo
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cc65500434
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Use csr_set to set stvec
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2024-08-21 10:12:41 +02:00 |
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Rodrigo Arias Mallo
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64cc2a982f
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Clear MIP before enabling timer
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2024-08-21 10:09:06 +02:00 |
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Rodrigo Arias Mallo
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90df8a3ccb
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Add stvec trap
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2024-08-21 10:03:19 +02:00 |
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Rodrigo Arias Mallo
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baf45e6749
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Dump more registers in PLIC test
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2024-08-21 09:53:39 +02:00 |
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Rodrigo Arias Mallo
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fd2b766760
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Improve progress print
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2024-08-21 09:39:00 +02:00 |
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Rodrigo Arias Mallo
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1faef5b452
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Don't enable machine interrupt
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2024-08-21 09:29:22 +02:00 |
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Rodrigo Arias Mallo
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b7287bd4df
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Port supervisor PLIC test to OpenSBI
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2024-08-21 09:25:07 +02:00 |
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